公开(公告)号：US20240244824A1

公开(公告)日：2024-07-18

申请号：US18427852

申请日：2024-01-31

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ken-Li Chen ,  Yifei Yan ,  Yu-Cheng Tung

IPC: H10B12/00 ,  H01L29/06

CPC classification number: H10B12/315 ,  H01L29/0649 ,  H10B12/0335 ,  H10B12/482

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.

公开(公告)号：US20240395605A1

公开(公告)日：2024-11-28

申请号：US18789716

申请日：2024-07-31

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/764 ,  H01L23/532 ,  H10B12/00

Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.

公开(公告)号：US12100617B2

公开(公告)日：2024-09-24

申请号：US18134036

申请日：2023-04-13

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/764 ,  H01L21/768 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5329 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

公开(公告)号：US20230144120A1

公开(公告)日：2023-05-11

申请号：US17573597

申请日：2022-01-11

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ken-Li Chen ,  Yifei Yan ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L29/06

CPC classification number: H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.

公开(公告)号：US20210375878A1

公开(公告)日：2021-12-02

申请号：US17317923

申请日：2021-05-12

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H01L27/108 ,  H01L23/532

Abstract: A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.

公开(公告)号：US11930631B2

公开(公告)日：2024-03-12

申请号：US17573597

申请日：2022-01-11

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ken-Li Chen ,  Yifei Yan ,  Yu-Cheng Tung

IPC: H10B12/00 ,  H01L29/06

CPC classification number: H10B12/315 ,  H01L29/0649 ,  H10B12/0335 ,  H10B12/482

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.

公开(公告)号：US20230255018A1

公开(公告)日：2023-08-10

申请号：US18134036

申请日：2023-04-13

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H10B12/00 ,  H01L23/532

CPC classification number: H10B12/315 ,  H01L23/5329 ,  H10B12/482 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

公开(公告)号：US11665885B2

公开(公告)日：2023-05-30

申请号：US17317923

申请日：2021-05-12

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H01L27/10 ,  H01L23/532

CPC classification number: H10B12/315 ,  H01L23/5329 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.