公开(公告)号：US20240412772A1

公开(公告)日：2024-12-12

申请号：US18376455

申请日：2023-10-04

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yifei Yan ,  Hui-Huang Chen ,  Chao-Wei Lin

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/4096 ,  H10B12/00

Abstract: A memory structure includes a substrate, a first device layer disposed on the substrate, a plurality of memory regions in the first device layer, a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions, a second device layer disposed between the substrate and the first device layer, and first peripheral regions and second peripheral regions in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions.

公开(公告)号：US11069774B2

公开(公告)日：2021-07-20

申请号：US16696765

申请日：2019-11-26

Applicant: Fujian Jinhua Integrated Circuit Co., LTD.

Inventor： Huixian Lai ,  Yu Cheng Tung ,  Chao-Wei Lin ,  Chiayi Chu

IPC: H01L29/06

Abstract: A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

公开(公告)号：US20240395605A1

公开(公告)日：2024-11-28

申请号：US18789716

申请日：2024-07-31

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/764 ,  H01L23/532 ,  H10B12/00

Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.

公开(公告)号：US12100617B2

公开(公告)日：2024-09-24

申请号：US18134036

申请日：2023-04-13

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/764 ,  H01L21/768 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5329 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

公开(公告)号：US12069851B2

公开(公告)日：2024-08-20

申请号：US17298315

申请日：2020-03-17

Applicant: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.

Inventor： Chung-Yen Chou ,  Chih-Yuan Chen ,  Qinfu Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Jen-Chieh Cheng ,  Jen-Kuo Wu ,  Huixian Lai

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/34

Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion. In this way, current leakage between word lines (WL) and the active areas (AA) can be mitigated.

公开(公告)号：US20240047519A1

公开(公告)日：2024-02-08

申请号：US18380616

申请日：2023-10-16

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Huixian Lai ,  Yu Cheng Tung ,  Chao-Wei Lin ,  Chiayi Chu

IPC: H01L29/06

CPC classification number: H01L29/0649

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

公开(公告)号：US20210225851A1

公开(公告)日：2021-07-22

申请号：US17151669

申请日：2021-01-19

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Huixian LAI ,  Chao-Wei Lin ,  Chia-Yi Chu

IPC: H01L27/108

Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.

公开(公告)号：US11824087B2

公开(公告)日：2023-11-21

申请号：US17349906

申请日：2021-06-16

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Huixian Lai ,  Yu Cheng Tung ,  Chao-Wei Lin ,  Chiayi Chu

IPC: H01L29/06

CPC classification number: H01L29/0649

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

公开(公告)号：US20210098571A1

公开(公告)日：2021-04-01

申请号：US16696765

申请日：2019-11-26

Applicant: Fujian Jinhua Integrated Circuit Co., LTD.

Inventor： Huixian Lai ,  Yu Cheng Tung ,  Chao-Wei Lin ,  Chiayi Chu

IPC: H01L29/06

Abstract: A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

公开(公告)号：US20230255018A1

公开(公告)日：2023-08-10

申请号：US18134036

申请日：2023-04-13

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H10B12/00 ,  H01L23/532

CPC classification number: H10B12/315 ,  H01L23/5329 ,  H10B12/482 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.