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    METHOD FOR DICING A SEMICONDUCTOR WAFER STRUCTURE
    1.
    发明公开
    METHOD FOR DICING A SEMICONDUCTOR WAFER STRUCTURE 审中-公开

    公开(公告)号：US20230317521A1

    公开(公告)日：2023-10-05

    申请号：US17709696

    申请日：2022-03-31

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shu-Hui Su

    IPC: H01L21/78 ,  H01L23/544

    CPC classification number: H01L21/78 ,  H01L23/544 ,  H01L2223/5448

    Abstract: The present disclosure relates to a method for forming an integrated chip. The method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. The method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. The method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.

    Method of making a semiconductor device including barrier layers for copper interconnect
    5.
    发明授权
    Method of making a semiconductor device including barrier layers for copper interconnect 有权
    制造包括铜互连的阻挡层的半导体器件的方法

    公开(公告)号：US08975749B2

    公开(公告)日：2015-03-10

    申请号：US14151857

    申请日：2014-01-10

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Nai-Wei Liu ,  Zhen-Cheng Wu ,  Cheng-Lin Huang ,  Po-Hsiang Huang ,  Yung-Chih Wang ,  Shu-Hui Su ,  Dian-Hau Chen ,  Yuh-Jier Mii

    IPC: H01L23/532 ,  H01L23/48 ,  H01L21/44 ,  H01L21/768

    CPC classification number: H01L21/76846 ,  H01L21/76831 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.

    Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成电介质层。 该方法还包括在电介质层中形成含铜层，其中含铜层具有第一部分和第二部分。 该方法还包括在含铜层的第一部分和电介质层之间形成第一阻挡层。 所述方法还包括在所述含铜层的第二部分和所述介电层之间的边界处形成第二阻挡层，其中所述第二阻挡层与所述电介质层的暴露部分相邻。 第一阻挡层是电介质层，第二阻挡层是金属氧化物层，并且含铜层的侧壁和第一阻挡层之间的边界不含第二阻挡层。

    Trench capacitor film scheme to reduce substrate warpage
    6.
    发明授权
    Trench capacitor film scheme to reduce substrate warpage 有权

    公开(公告)号：US12199139B2

    公开(公告)日：2025-01-14

    申请号：US17861755

    申请日：2022-07-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ting-Chen Hsu ,  Hsin-Li Cheng ,  Jyun-Ying Lin ,  Yingkit Felix Tsui ,  Shu-Hui Su ,  Shi-Min Wu

    IPC: H10B12/00 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

    Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

    TRENCH CAPACITOR FILM SCHEME TO REDUCE SUBSTRATE WARPAGE
    8.
    发明公开
    TRENCH CAPACITOR FILM SCHEME TO REDUCE SUBSTRATE WARPAGE 审中-公开

    公开(公告)号：US20240014254A1

    公开(公告)日：2024-01-11

    申请号：US17861755

    申请日：2022-07-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ting-Chen Hsu ,  Hsin-Li Cheng ,  Jyun-Ying Lin ,  Yingkit Felix Tsui ,  Shu-Hui Su ,  Shi-Min Wu

    IPC: H01L49/02

    CPC classification number: H01L28/91 ,  H01L28/75

    Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

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