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公开(公告)号：US20230378251A1
公开(公告)日：2023-11-23
申请号：US18362146
申请日：2023-07-31
Inventor： Hsin-Li Cheng , Jyun-Ying Lin , Alexander Kalnitsky , Shih-Fen Huang , Shu-Hui Su , Ting-Chen Hsu , Tuo-Hsin Chien , Felix Ying-Kit Tsui , Shi-Min Wu , Yu-Chi Chang
IPC: H10N69/00 , H01L21/3213 , H01L21/02 , H01L29/66 , H01L21/764 , H01L29/94 , H01L23/00
CPC classification number: H01L28/91 , H01L21/32139 , H01L28/92 , H01L21/02164 , H01L29/66181 , H01L21/764 , H01L29/945 , H01L23/562 , H01L21/02236
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.
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公开(公告)号：US20240147689A1
公开(公告)日：2024-05-02
申请号：US18173489
申请日：2023-02-23
Inventor： Ming-Hsun Lin , Jyun-Ying Lin
CPC classification number: H10B12/0387 , H01L29/66181 , H01L29/945
Abstract: Integrated circuits (ICs) and methods are provided. An IC includes a charge-storing device. The charge-storing device includes a first charge-storing stack extending into a substrate, and a second charge-storing stack extending into the substrate and adjacent to the first charge-storing stack along a first direction. The first charge-storing stack and the second charge-storing stack extend lengthwise along a second direction perpendicular to the first direction, and the first charge-storing stack and the second charge-storing stack have an offset along the second direction, the offset being greater than zero.
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公开(公告)号：US08853079B2
公开(公告)日：2014-10-07
申请号：US14151862
申请日：2014-01-10
Inventor： Jyun-Ying Lin , Chun-Yao Ko , Ting-Chen Hsu
IPC: H01L21/44 , H01L23/525 , H01L21/768
CPC classification number: H01L21/76886 , H01L23/5256 , H01L2924/0002 , H01L2924/00
Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.
Abstract translation: 形成器件的方法包括形成在第一节点和第二节点之间连续延伸的含硅线。 在含硅线上形成第一含硅化物部分和第二硅化物部分。 第一含硅化物部分与第二硅化物含有部分分开预定距离，并且预定距离基本上等于或小于含硅线的长度。
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公开(公告)号：US20250063744A1
公开(公告)日：2025-02-20
申请号：US18939603
申请日：2024-11-07
Inventor： Hsin-Li Cheng , Jyun-Ying Lin , Alexander Kalnitsky , Shih-Fen Huang , Shu-Hui Su , Ting-Chen Hsu , Tuo-Hsin Chien , Felix Ying-Kit Tsui , Shi-Min Wu , Yu-Chi Chang
IPC: H01L21/02 , H01L21/3213 , H01L21/764 , H01L23/00 , H01L29/66 , H01L29/94
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.
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公开(公告)号：US12199139B2
公开(公告)日：2025-01-14
申请号：US17861755
申请日：2022-07-11
Inventor： Ting-Chen Hsu , Hsin-Li Cheng , Jyun-Ying Lin , Yingkit Felix Tsui , Shu-Hui Su , Shi-Min Wu
Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.
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Patent Agency Ranking
公开(公告)号：US12176387B2
公开(公告)日：2024-12-24
申请号：US18362146
申请日：2023-07-31
Inventor： Hsin-Li Cheng , Jyun-Ying Lin , Alexander Kalnitsky , Shih-Fen Huang , Shu-Hui Su , Ting-Chen Hsu , Tuo-Hsin Chien , Felix Ying-Kit Tsui , Shi-Min Wu , Yu-Chi Chang
IPC: H01L29/94 , H01L21/02 , H01L21/3213 , H01L21/764 , H01L23/00 , H01L29/66 , H01L49/02
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.
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公开(公告)号：US20240014254A1
公开(公告)日：2024-01-11
申请号：US17861755
申请日：2022-07-11
Inventor： Ting-Chen Hsu , Hsin-Li Cheng , Jyun-Ying Lin , Yingkit Felix Tsui , Shu-Hui Su , Shi-Min Wu
IPC: H01L49/02
Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.
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公开(公告)号：US11769792B2
公开(公告)日：2023-09-26
申请号：US17370067
申请日：2021-07-08
Inventor： Hsin-Li Cheng , Jyun-Ying Lin , Alexander Kalnitsky , Shih-Fen Huang , Shu-Hui Su , Ting-Chen Hsu , Tuo-Hsin Chien , Felix Ying-Kit Tsui , Shi-Min Wu , Yu-Chi Chang
IPC: H01L29/94 , H01L23/00 , H01L29/66 , H01L21/02 , H01L21/3213 , H01L21/764 , H01L49/02
CPC classification number: H01L28/91 , H01L21/02164 , H01L21/02236 , H01L21/32139 , H01L21/764 , H01L23/562 , H01L28/92 , H01L29/66181 , H01L29/945
Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.
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公开(公告)号：US20210343881A1
公开(公告)日：2021-11-04
申请号：US17370067
申请日：2021-07-08
Inventor： Hsin-Li Cheng , Jyun-Ying Lin , Alexander Kalnitsky , Shih-Fen Huang , Shu-Hui Su , Ting-Chen Hsu , Tuo-Hsin Chien , Felix Ying-Kit Tsui , Shi-Min Wu , Yu-Chi Chang
IPC: H01L29/94 , H01L49/02 , H01L23/00 , H01L29/66 , H01L21/02 , H01L21/3213 , H01L21/764
Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.
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公开(公告)号：US08962439B2
公开(公告)日：2015-02-24
申请号：US14301443
申请日：2014-06-11
Inventor： Jyun-Ying Lin , Chun-Yao Ko , Ting-Chen Hsu
IPC: H01L21/20 , H01L23/525
CPC classification number: H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
Abstract: A method of programming a memory cell includes causing a current to flow through a first silicide-containing portion and a second silicide-containing portion of the memory cell; and causing, by the current, an electron-migration effect to form an extended silicide-containing portion within the gap such that the memory cell is converted from a first state into a second state. The memory cell includes a silicon-containing line continuously extending between a first region and a second region; the first silicide-containing portion over the silicon-containing line and adjacent to the first region; and the second silicide-containing portion over the silicon-containing line and adjacent to the second region. The first silicide-containing portion and the second silicide-containing portion are separated by a gap if the memory cell is at the first state. The extended silicide-containing portion extends from the second silicide-containing portion towards the first silicide-containing portion.
Abstract translation: 编程存储器单元的方法包括使电流流过存储单元的第一含硅化物的部分和第二硅化物的部分; 并且通过电流使电子迁移效应在间隙内形成延伸的含硅化物的部分，使得存储单元从第一状态转换为第二状态。 存储单元包括在第一区域和第二区域之间连续延伸的含硅线; 所述含硅线上方的第一硅化物部分和所述第一区域相邻; 以及位于含硅线上方并与第二区相邻的第二硅化物部分。 如果存储单元处于第一状态，则第一硅化物含量部分和第二硅化物部分被间隙分开。 所述延伸的含硅化物的部分从所述第二硅化物含有部分朝向所述第一含硅化物部分延伸。
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