公开(公告)号：US12237230B2

公开(公告)日：2025-02-25

申请号：US17238778

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Yu Lai ,  Jyun-Chih Lin ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Wei Hao Lu ,  Li-Li Su

IPC: H01L21/8238 ,  H01L21/764 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

公开(公告)号：US11063152B2

公开(公告)日：2021-07-13

申请号：US16547191

申请日：2019-08-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US20210057567A1

公开(公告)日：2021-02-25

申请号：US16547191

申请日：2019-08-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US20220122893A1

公开(公告)日：2022-04-21

申请号：US17238778

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Yu Lai ,  Jyun-Chih Lin ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Wei Hao Lu ,  Li-Li Su

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

公开(公告)号：US20230395434A1

公开(公告)日：2023-12-07

申请号：US18447459

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Yu Lai ,  Jyun-Chih Lin ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Wei Hao Lu ,  Li-Li Su

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/764 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66545 ,  H01L29/6653 ,  H01L21/764

Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.