知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

241 条记录 (耗时 0.024 秒)

    Power validation based on power assertion specification
    3.
    发明授权
    Power validation based on power assertion specification 有权

    公开(公告)号：US11907630B1

    公开(公告)日：2024-02-20

    申请号：US16906771

    申请日：2020-06-19

    申请人： Synopsys, Inc.

    发明人： Jitendra Kumar Gupta ,  Alexander John Wakefield

    IPC分类号： G06F30/20 ,  G06F30/331 ,  G06F16/9035 ,  G06F30/337 ,  G06F119/06

    CPC分类号： G06F30/331 ,  G06F16/9035 ,  G06F30/337 ,  G06F2119/06

    摘要： A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

    Solver creation tool for system simulation
    6.
    发明授权
    Solver creation tool for system simulation 有权

    公开(公告)号：US11755800B2

    公开(公告)日：2023-09-12

    申请号：US17345482

    申请日：2021-06-11

    申请人： University of South Carolina

    发明人： Matthew A. Milton ,  Andrea Benigni

    IPC分类号： G06F30/23 ,  G06F30/331 ,  G06F111/20

    CPC分类号： G06F30/331 ,  G06F2111/20

    摘要： A method for generating a simulator of a target system includes parsing data defining operational components and component parameters, searching for and obtaining model code definitions within a library database, customizing the model code definitions based on the component parameters, constructing a system model, and generating solver code based the customized model code definitions of the target system. The solver code may be indicative of input and output operation of the target system. The method may also include concatenating the system model with the solver code to form a solver function definition for the target system, and converting the solver function definition into an field programmable gate array (FPGA) core or central processing unit (CPU) core for execution on a simulation device for the target system.

    FPGA-Based Parallel Equalization Method
    7.
    发明公开
    FPGA-Based Parallel Equalization Method 审中-公开

    公开(公告)号：US20230251973A1

    公开(公告)日：2023-08-10

    申请号：US17960212

    申请日：2022-10-05

    申请人： HDU Fuyang Electronic Information Research Institute Co., Ltd. ,  HangZhou DianZi University

    发明人： Zhiqun CHENG ,  Qingran SUN ,  Chao LE

    IPC分类号： G06F12/0884 ,  G06F30/331

    CPC分类号： G06F12/0884 ,  G06F30/331

    摘要： A field programmable gate array (FPGA)-based parallel equalization method is provided. The method implements efficient equalization of communication data by means of a parallel pipeline filter structure and through a least mean square (LMS) algorithm capable of dynamically adjusting a step. Firstly, a tap coefficient of an equalization filter is calculated through the LMS algorithm capable of dynamically adjusting an iteration factor. Secondly, the efficiency of FPGA data processing is improved through a multistage pipeline and a multi-channel parallel data processing. According to the present disclosure, in each clock cycle, there are M channels of data inputted into the equalization filter in parallel, and at the same time, there are also M channels of data outputted in parallel, and thus the FPGA can efficiently perform equalization processing on data acquired by a high-speed analog-to-digital converter (ADC) through the parallel pipeline method.

    Structural matching for fast re-synthesis of electronic circuits
    10.
    发明授权
    Structural matching for fast re-synthesis of electronic circuits 有权

    公开(公告)号：US11599700B2

    公开(公告)日：2023-03-07

    申请号：US17247085

    申请日：2020-11-30

    申请人： The Regents of the University of California

    发明人： Rafael Possignolo ,  Jose Renau

    IPC分类号： G06F30/327 ,  G06F30/331 ,  G06F30/392 ,  G06F30/398 ,  G06F30/396

    摘要： Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components. A different second placed and routed netlist (PR2) is generated for the second circuit by deriving new placement and routing for only for non-matching components in SN2.