公开(公告)号：US12271669B1

公开(公告)日：2025-04-08

申请号：US17709192

申请日：2022-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Assaf Fainer ,  Simaan Bahouth ,  Max Chvalevsky ,  Itai Kahana

IPC: G06F30/30 ,  G06F30/3323 ,  G06F30/367

Abstract: Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

公开(公告)号：US11768990B1

公开(公告)日：2023-09-26

申请号：US17305043

申请日：2021-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Max Chvalevsky ,  Benzi Denkberg ,  Guy Nakibly

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/331 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/331 ,  G06F30/392 ,  G06F30/398

Abstract: An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.