公开(公告)号：US11361140B1

公开(公告)日：2022-06-14

申请号：US17094790

申请日：2020-11-10

申请人： Synopsys, Inc.

发明人： Jitendra Kumar Gupta ,  Ksenia Roze ,  Xun Liu ,  Paul Chang ,  Lan Luo

IPC分类号： G06F30/3953

摘要： Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

公开(公告)号：US11907630B1

公开(公告)日：2024-02-20

申请号：US16906771

申请日：2020-06-19

申请人： Synopsys, Inc.

发明人： Jitendra Kumar Gupta ,  Alexander John Wakefield

IPC分类号： G06F30/20 ,  G06F30/331 ,  G06F16/9035 ,  G06F30/337 ,  G06F119/06

CPC分类号： G06F30/331 ,  G06F16/9035 ,  G06F30/337 ,  G06F2119/06

摘要： A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

公开(公告)号：US11334700B1

公开(公告)日：2022-05-17

申请号：US16875238

申请日：2020-05-15

申请人： Synopsys, Inc.

发明人： Alexander John Wakefield ,  Jitendra Kumar Gupta

IPC分类号： G06F17/10 ,  G06F30/367 ,  G06F119/06 ,  G06F119/08

摘要： A simulation application can be executed by a computer system to develop thermal maps for an electronic architectural design. The simulation application can simulate the electronic architectural design over time. The simulation application can capture electronic signals from the electronic architectural design as the electronic architectural design is being simulated over time. The simulation application can determine power consumptions of the electronic architectural design over time from the electronic signals. The simulation application can derive temperatures of the electronic architectural design over time from the power consumptions. The simulation application can map the temperatures onto an electronic circuit design real estate of the electronic architectural design to develop the thermal maps over time.