公开(公告)号：US12105139B2

公开(公告)日：2024-10-01

申请号：US17565284

申请日：2021-12-29

申请人： Advanced Micro Devices, Inc.

发明人： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3183

CPC分类号： G01R31/287 ,  G01R31/2879 ,  G01R31/31718 ,  G01R31/318314

摘要： A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.

公开(公告)号：US20240319268A1

公开(公告)日：2024-09-26

申请号：US18189859

申请日：2023-03-24

申请人： QUALCOMM Incorporated

发明人： Gaurav VERMA ,  Saksham TANDON

IPC分类号： G01R31/317 ,  B60L3/00 ,  G01R31/3183 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/16

CPC分类号： G01R31/31724 ,  B60L3/0084 ,  G01R31/318335 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/16

摘要： Aspects of the present disclosure provide a method generally including obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions, applying a compression scheme to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and data field of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes, and storing the compressed BIST patterns.

公开(公告)号：US20240302432A1

公开(公告)日：2024-09-12

申请号：US18597499

申请日：2024-03-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hobin SONG ,  Juyun Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Sooeun Lee ,  Insik Hwang

IPC分类号： G01R31/3183 ,  G01R31/317 ,  G01R31/3187 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081

CPC分类号： G01R31/318328 ,  G01R31/31724 ,  G01R31/3187 ,  H03K5/13 ,  H03L7/0807 ,  H03K2005/00052 ,  H03L7/0812

摘要： A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

公开(公告)号：US20240248135A1

公开(公告)日：2024-07-25

申请号：US18304568

申请日：2023-04-21

申请人： Cisco Technology, Inc.

发明人： Fabio Bottoni ,  Alessandro Cavaciuti

IPC分类号： G01R31/3183

CPC分类号： G01R31/318385 ,  G01R31/318371

摘要： Techniques are provided for generating a physical test pattern that is framed within an Forward Error Correction (FEC)-encoded stream or sequence. Accordingly, in one embodiment, a method is provided that includes obtaining a physical layer test pattern for testing operation of a device; generating an FEC framed test pattern that embeds the physical layer test pattern into an FEC-encoded stream; and applying the FEC framed test pattern to the transceiver device to test physical layer operation of the device and to obtain FEC error statistics.

公开(公告)号：US20240201257A1

公开(公告)日：2024-06-20

申请号：US18536973

申请日：2023-12-12

申请人： University of Florida Research Foundation, Incorporated

发明人： Greg M. Stitt ,  Swarup Bhunia ,  Naren Vikram Raj Masna ,  Aritra Dasgupta

IPC分类号： G01R31/3183 ,  G01R31/3185

CPC分类号： G01R31/318307 ,  G01R31/318525 ,  G01R31/318536

摘要： A method and system are directed to testing reconfigurable hardware designs, the method comprising inserting a scan chain into a reconfigurable hardware design associated with an integrated circuit comprising a redacted design; generating, using an automatic test pattern generation (ATPG) system, one or more test patterns and one or more bitstreams; receiving one or more primary outputs and contents of the scan chain from the reconfigurable hardware design by applying the one or more test patterns and the one or more bitstreams to the reconfigurable hardware design based on an ATPG test method of a plurality of ATPG test methods and a test architecture of a plurality of test architectures; comparing the one or more outputs and contents of the scan chain with one or more respective expected outcomes; and determining one or more faults associated with the reconfigurable hardware design based on the comparison.

公开(公告)号：US12007439B1

公开(公告)日：2024-06-11

申请号：US18149165

申请日：2023-01-03

申请人： Winbond Electronics Corp.

发明人： Kuo-Min Liao ,  Tien-Yu Liao ,  Chien-Han Liao

IPC分类号： G01R31/3183 ,  G01R31/3193

CPC分类号： G01R31/318371 ,  G01R31/31932 ,  G01R31/31935

摘要： A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.

公开(公告)号：US11983474B1

公开(公告)日：2024-05-14

申请号：US17561371

申请日：2021-12-23

申请人： Synopsys, Inc.

发明人： Parijat Biswas ,  Badri Gopalan ,  Enzhi Ni ,  Danish Jawed ,  Ying Chen ,  Jiang Chen

IPC分类号： G06F30/30 ,  G01R31/3183 ,  G06F30/323 ,  G06F30/3308

CPC分类号： G06F30/3308 ,  G01R31/31835 ,  G01R31/318357 ,  G06F30/323

摘要： A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified connections in a database, and using, by a processor, connections retrieved from the database to simulate and verify the coverage areas of the IC design.

公开(公告)号：US20240094287A1

公开(公告)日：2024-03-21

申请号：US18229965

申请日：2023-08-03

申请人： ADVANTEST CORPORATION

发明人： Edmundo De La Puente ,  Linden Hsu ,  Mei-Mei Su ,  Marilyn Kushnick

IPC分类号： G01R31/317 ,  G01R31/3183

CPC分类号： G01R31/31721 ,  G01R31/318307

摘要： A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.

公开(公告)号：US11906583B2

公开(公告)日：2024-02-20

申请号：US17545520

申请日：2021-12-08

申请人： Rohde & Schwarz GmbH & Co. KG

发明人： Kevin Guo ,  Hong Jin Kim

IPC分类号： G01R31/3183 ,  G01R31/317 ,  G01R31/3185

CPC分类号： G01R31/318314 ,  G01R31/31706 ,  G01R31/31713 ,  G01R31/318536

摘要： The present invention relates to a method for testing a device under test. A component of the device under test generates or receives a bus signal, wherein the bus signal comprises a first data signal or a second data signal, and wherein an amplitude of the first data signal is different from an amplitude of the second data signal. A measurement instrument measures an amplitude of the bus signal. Further, it is determined whether the bus signal comprises the first data signal or the second data signal, based on the measured amplitude of the bus signal.

公开(公告)号：US11867760B2

公开(公告)日：2024-01-09

申请号：US17442263

申请日：2021-06-17

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Hao He

IPC分类号： G11C7/00 ,  G01R31/3181 ,  G01R31/28 ,  G01R31/3183

CPC分类号： G01R31/31813 ,  G01R31/2889 ,  G01R31/318314

摘要： The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.