-
公开(公告)号：US12079098B2
公开(公告)日：2024-09-03
申请号：US17135790
申请日：2020-12-28
IPC分类号： G06F11/273 , G01R31/317 , G06F13/42
CPC分类号： G06F11/2736 , G01R31/31724 , G06F13/4282 , G06F2213/0026 , G06F2213/0028
摘要： An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.
-
公开(公告)号：US20210302498A1
公开(公告)日：2021-09-30
申请号：US17195342
申请日：2021-03-08
发明人： Mei-Mei Su , Seth Craighead
IPC分类号： G01R31/317 , G01R31/3185
摘要： Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a tester system diagnostic method includes forwarding test signals to a loopback component; receiving the test signals from the loopback component; and analyzing the test signals to diagnose whether or not the test system is experiencing problems associated with electrostatic discharges, including analysis of eye scan configuration data corresponding to characteristics of the test signals. In one exemplary implementation, analyzing the eye scan configuration data, including analyzing symmetry of a graphical representation (e.g., eye pattern, eye diagram, etc.) of the eye scan configuration data with respect to a horizontal graphical representation axis.
-
公开(公告)号：US11099228B2
公开(公告)日：2021-08-24
申请号：US15455064
申请日：2017-03-09
发明人： Mei-Mei Su
IPC分类号： G01R31/28
摘要： Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a primitive configured to control testing of a device under test (DUT) and a device interface board (DIB). The device interface board comprises: a loadboard, an environmental control component and a device under test access interface. The loadboard is configured to selectively couple with a device under test and a primitive. The environmental control component is configured to control environmental conditions. The device under test access interface is configured to allow robotic manipulation of the device under test. The manipulation can include selectively coupling the device under test to the loadboard. The device under test access interface can be configured to enable unobstructed access for robotic manipulation of the device under test.
-
公开(公告)号：US11002787B2
公开(公告)日：2021-05-11
申请号：US15913673
申请日：2018-03-06
发明人： Roland Wolff , Mei-Mei Su , Ben Rogel-Favila
摘要： A scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.
-
公开(公告)号：US20240118340A1
公开(公告)日：2024-04-11
申请号：US18230003
申请日：2023-08-03
发明人： Edmundo De La Puente , Mei-Mei Su , Srdjan Malisic
IPC分类号： G01R31/3181 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31813 , G01R31/31724 , G01R31/318544
摘要： A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.
-
6.发明申请公开(公告)号：US20190354453A1
公开(公告)日：2019-11-21
申请号：US15981634
申请日：2018-05-16
发明人： Linden Hsu , Ben Rogel-Favila , Michael Jones , Duane Champoux , Mei-Mei Su
摘要： A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.
-
公开(公告)号：US10288681B2
公开(公告)日：2019-05-14
申请号：US15982910
申请日：2018-05-17
发明人： Duane Champoux , Mei-Mei Su
IPC分类号： G01R31/26 , G01R35/00 , G01R31/317 , G01R31/319 , G06F11/263
摘要： An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.
-
公开(公告)号：US09933454B2
公开(公告)日：2018-04-03
申请号：US14515417
申请日：2014-10-15
发明人： Ben Rogel-Favila , Roland Wolff , Eric Kushnick , James Fishman , Mei-Mei Su
CPC分类号： G01R1/04 , B25J9/0084 , B25J9/0093 , G01R1/44 , G01R31/26 , G01R31/2801 , G01R31/2851 , G01R31/2893 , G11B19/048
摘要： In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.
-
公开(公告)号：US20240094287A1
公开(公告)日：2024-03-21
申请号：US18229965
申请日：2023-08-03
发明人： Edmundo De La Puente , Linden Hsu , Mei-Mei Su , Marilyn Kushnick
IPC分类号： G01R31/317 , G01R31/3183
CPC分类号： G01R31/31721 , G01R31/318307
摘要： A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.
-
公开(公告)号：US20210302501A1
公开(公告)日：2021-09-30
申请号：US17219297
申请日：2021-03-31
发明人： Mei-Mei Su , Seth Craighead
IPC分类号： G01R31/319 , G01R31/28
摘要： Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances. In one exemplary implementation, the test equipment component is a test control component (e.g., a field programmable gate array (FPGA), etc.).
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.017 秒)
