Abstract:
A potential difference early-warning circuit, comprising: a sensing resistor (R2), (PCB GND); a first MOS (M1), a drain of the first MOS being connected to the sensing resistor (R2), and a source of the first MOS (M1) being connected to a safety ground (GND); an operational amplifier (U1A), a positive input end of the operational amplifier being connected to one end of the sensing resistor (R2), and a negative input end of the operational amplifier (U1A) being connected to the other end of the sensing resistor (R2); a second MOS (M2), a gate of the second MOS (M2) being connected to an output end of the operational amplifier (U1A), and a source of the second MOS (M2) being connected to the signal ground; and a controller, a first input end of the controller being connected to the drain of the second MOS (M2), and an output end of the controller being connected to the gate of the second MOS (M2).
Abstract:
Systems, methods, and devices for monitoring operation of industrial equipment are disclosed. In one embodiment, a monitoring system is provided that includes a passive backplane and one more functional circuits that can couple to the backplane. Each of the functional circuits that are coupled to the backplane can have access to all data that is delivered to the backplane. Therefore, resources (e.g., computing power, or other functionality) from each functional circuits can be shared by all active functional circuits that are coupled to the backplane. Because resources from each of the functional circuits can be shared, and because the functional circuits can be detachably coupled to the backplane, performance of the monitoring systems can be tailored to specific applications. For example, processing power can be increased by coupling additional processing circuits to the backplane.
Abstract:
One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.
Abstract:
The present disclosure relates to an electronic unit including at least one component and a printed circuit board, wherein the at least one component has at least one terminal, wherein the printed circuit board has at least one first contact surface and at least one second contact surface, wherein the at least one first contact surface and the at least one second contact surface are spaced apart from one another, wherein the at least one terminal is joined to the at least two contact surfaces by at least one solder joint. The present disclosure further relates to a method for testing at least one state of an electronic unit.
Abstract:
The present disclosure relates to a system and method for health monitoring and early warning for an electronic device. A sensor is used to monitor a physical parameter of a circuit board of a host electronic system of the electronic device to acquire sensor data, and transmit the acquired sensor data to an embedded control device. The sensor data includes at least one of current data, vibration data, temperature data and voltage data. The embedded control device is used to extract a feature from the sensor data to acquire feature data, and perform real-time analysis and prediction based on the feature data to obtain and display a prediction result. In this way, the user can be provided with real-time health monitoring and real-time prediction information for the host electronic system circuit board.
Abstract:
In one embodiment, a universal test container can include a universal external electrical interface configured to couple to each of a plurality of different devices to test. In addition, the universal test container is configured to enclose each of the plurality of different devices to test.
Abstract:
In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.
Abstract:
A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.
Abstract:
A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.
Abstract:
A method for detecting electrical disconnections of a chip during testing under environmental conditions includes providing n monitor connections on a chip from which a voltage or current can be sensed during testing of the chip under environmental conditions, where n is an integer of at least one. M sensing connections are provided on the chip, where m>n. An electrical circuit for electrically connects the n monitor connections with the m sensing connections. The electrical circuit has a characteristic that changes when one or more of the m sensing connections is disconnected from its corresponding contact on the printed circuit board or chip socket. The electrical circuit is monitored via the n monitor connections during the testing. It is determined based on changes in the characteristic, whether one or more of the m sensing connections is disconnected from the printed circuit board or chip socket.