System for the phase locking synthesized high frequency pulses to a low
frequency signal
    1.
    发明授权
    System for the phase locking synthesized high frequency pulses to a low frequency signal 失效
    用于锁相的系统将高频脉冲合成为低频信号

    公开(公告)号:US4213156A

    公开(公告)日:1980-07-15

    申请号:US899273

    申请日:1978-04-24

    CPC classification number: H04N1/36

    Abstract: A source of clock pulses is coupled to a synthesizer of higher frequency pulses which comprises a frequency divider which is reset in response to each of the higher frequency pulses. A lower frequency square wave signal is applied to circuitry for generating blanking pulses and low frequency pulses to be inserted periodically between the higher frequency pulses after the blanking pulses are applied to the synthesizer.

    Abstract translation: 时钟脉冲源耦合到较高频率脉冲的合成器,其包括响应于每个较高频率脉冲复位的分频器。 较低频率的方波信号被施加到用于产生消隐脉冲和低频脉冲的电路,以便在将消隐脉冲施加到合成器之后周期性地插入较高频率脉冲之间。

    Sync signal generator with memorization of phase detection output
    2.
    发明授权
    Sync signal generator with memorization of phase detection output 失效
    同步信号发生器存储相位检测输出

    公开(公告)号:US4122488A

    公开(公告)日:1978-10-24

    申请号:US783773

    申请日:1977-04-01

    Applicant: Tsuneo Mikado

    Inventor: Tsuneo Mikado

    CPC classification number: H03L7/146 H04N5/12

    Abstract: A television synchronizing signal generator includes a synchronizing signal separator circuit for separating a synchronizing signal from a video signal, an oscillator the oscillatory frequency of which is controllable, a phase discriminator for discriminating outputs of the synchronizing signal separator circuit and the oscillator, a memory circuit for memorizing an output of the phase discriminator, a switching circuit for applying alternatively the output of the phase discriminator and the output of the memory as a control signal to the oscillator to control the oscillatory frequency thereof, and an input state detector for detecting the input amplitude and noise state of the video signal such that the switching action of the switching circuit is controlled in accordance with the output of the input state detector. With such a generator, a stable picture can be obtained in a television receiver, even although the received video signal is temporarily abnormal.

    Abstract translation: 电视同步信号发生器包括用于从视频信号中分离同步信号的同步信号分离器电路,其振荡频率可控的振荡器,用于鉴别同步信号分离器电路和振荡器的输出的相位鉴别器,存储器电路 用于存储相位鉴别器的输出;切换电路,用于将相位鉴别器的输出和存储器的输出作为控制信号交替施加到振荡器以控制其振荡频率;以及输入状态检测器,用于检测输入 振幅和噪声状态,使得根据输入状态检测器的输出来控制开关电路的开关动作。 使用这样的发生器,即使接收到的视频信号暂时异常,也可以在电视接收机中获得稳定的图像。

    Phase locked loop exciter generator for high frequency transmitter
    3.
    发明授权
    Phase locked loop exciter generator for high frequency transmitter 失效
    用于高频发射机的锁相环激励器发生器

    公开(公告)号:US4107612A

    公开(公告)日:1978-08-15

    申请号:US683383

    申请日:1976-05-05

    Abstract: A phase locked loop signal generator is especially adapted for synthesizing a selectable frequency signal for exciting an HF radio frequency transmitter to transmit over the seven marine telegraph bands. The signal generator includes an oscillator for providing a highly stable frequency standard. Another signal generator is responsive to the frequency standard and to frequency selector signals input by the operator for generating an exciter signal which is coupled to the transmitter for effecting the RF transmission within a predetermined frequency range. The exciter signal generator includes: a reference dividing circuit programmable in response to the frequency selector signals for providing a reference frequency signal having a frequency which is a fractional part of that of the frequency standard; a phase locked loop circuit having a frequency divider in the feedback loop which is responsive to the reference frequency signal for producing an intermediate signal having a frequency which is a multiple of that of the reference frequency signal; and an output divider circuit is coupled to the phase locked loop circuit and is responsive to the frequency selector signal for generating the exciter signal to be at a frequency which is a fractional value of that of the intermediate signal. By varying the frequency selector signal, over 5000 transmitting frequencies are available using a conventional harmonic-related transmitter.

    Abstract translation: 锁相环信号发生器特别适用于合成用于激发HF射频发射器的可选频率信号,以在七个海洋电报频带上传输。 信号发生器包括用于提供高度稳定的频率标准的振荡器。 另一信号发生器响应于频率标准和操作者输入的频率选择器信号,用于产生耦合到发射器的激励器信号,以在预定频率范围内进行RF传输。 励磁信号发生器包括:参考分频电路,可响应于频率选择器信号而编程,用于提供频率为频率标准频率的一部分频率的参考频率信号; 一个锁相环电路,在反馈回路中具有分频器,该分频器响应于参考频率信号,用于产生频率为基准频率信号倍数的中间信号; 并且输出分频器电路耦合到锁相环电路,并且响应于频率选择器信号以产生激励器信号为处于与中间信号的分数值的分数值的频率。 通过改变频率选择器信号,使用传统的谐波相关发射机可以获得超过5000个发射频率。

    Delay line oscillator locked to a selected frequency of a chirp delay
line
    4.
    发明授权
    Delay line oscillator locked to a selected frequency of a chirp delay line 失效
    延迟线振荡器锁定到啁啾延迟线的选定频率

    公开(公告)号:US4100511A

    公开(公告)日:1978-07-11

    申请号:US799085

    申请日:1977-05-20

    CPC classification number: H03B5/326

    Abstract: An oscillator uses a delay line in a feedback loop to determine its frequency of operation. As the loop is capable of sustaining oscillations at more than one frequency the desired frequency is generated by an auxiliary delay line and is gated into loop at the correct instant by gating circuitry C.

    Abstract translation: 振荡器在反馈回路中使用延迟线来确定其工作频率。 由于环路能够在多于一个频率下维持振荡,所以需要的频率由辅助延迟线产生,并且通过选通电路C在正确的时刻门控成环路。

    Stabilized oscillator with output having high spectral purity
    5.
    发明授权
    Stabilized oscillator with output having high spectral purity 失效
    稳定的振荡器具有高光谱纯度的输出

    公开(公告)号:US3824485A

    公开(公告)日:1974-07-16

    申请号:US35536873

    申请日:1973-04-30

    Inventor: ASHLEY J PALKA F

    CPC classification number: H03L7/24

    Abstract: A stable low-noise high frequency signal source comprises a primary high frequency generator stabilized by a high-qualityfactor transmission resonator, the primary generator output also being injection phase locked by a stable secondary high frequency quartz crystal controlled generator.

    Abstract translation: 稳定的低噪声高频信号源包括由高品质因子传输谐振器稳定的初级高频发生器,主发生器输出也由稳定的次级高频石英晶体控制发生器注入锁相。

    Phase lock loop for a voltage controlled oscillator
    6.
    发明授权
    Phase lock loop for a voltage controlled oscillator 失效
    电压控制振荡器的相位锁定环

    公开(公告)号:US3775695A

    公开(公告)日:1973-11-27

    申请号:US3775695D

    申请日:1968-12-27

    Inventor: HILL C

    CPC classification number: H03L7/12

    Abstract: A phase locked voltage controlled oscillator having an automatic sweep and lock-up circuit employing a unijunction transistor relaxation oscillator as the controlling device in the circuit.

    Abstract translation: 一种锁相压控振荡器,其具有采用单结晶体管弛豫振荡器作为电路中的控制装置的自动扫描和锁定电路。

    Frequency synthesizer
    7.
    发明授权
    Frequency synthesizer 失效
    频率合成器

    公开(公告)号:US3657664A

    公开(公告)日:1972-04-18

    申请号:US3657664D

    申请日:1970-10-02

    Inventor: BRACK WERNER

    CPC classification number: H03L7/187

    Abstract: A frequency synthesizer having a phase lock loop for regulating a voltage controlled oscillator with reference to a stable oscillator frequency. The desired frequency is set on decade switches. An encoder converts the frequency value to a binary coded decimal equivalent nine''s complement number and presets a decade counter. An offset frequency is preintroduced into the counter by fixing the maximum count. Upon counting the maximum count, a shift register is triggered and during the shifting operation, the system is reset. The maximum count is reduced by the number of stages in the shift register. A steering voltage generator incorporating a staircase generator and an electronically switched filter is placed in parallel with the phase lock loop, and provides a coarse tuning of the voltage controlled oscillator.

    Abstract translation: 一种频率合成器,具有参考稳定的振荡器频率来调节压控振荡器的锁相环。 期望的频率在十年开关上设置。 编码器将频率值转换为二进制编码十进制等效九进制补码,并预置十进位计数器。 偏移频率通过固定最大计数被预先引入计数器。 在计数最大计数时,触发移位寄存器,在移位操作期间,系统复位。 最大计数减少移位寄存器中的级数。 结合了阶梯发生器和电子开关滤波器的转向电压发生器与锁相环并联放置,并提供压控振荡器的粗调。

    Frequency dividing system
    8.
    发明授权
    Frequency dividing system 失效
    频率分配系统

    公开(公告)号:US3559092A

    公开(公告)日:1971-01-26

    申请号:US3559092D

    申请日:1968-09-09

    Applicant: TEKTRONIX INC

    Inventor: ROTH STEPHEN A

    CPC classification number: H03L7/183 H04N5/06

    Abstract: A GIVEN SIGNAL IS DERIVED IN ACCURATELY TIMED RELATION WITH A HIGHER FREQUENCY SIGNAL, WHEREIN THE FREQUENCY OF THE LATTER SIGNAL IS OTHER THAN AN INTEGRAL MULTIPLE OF THE FREQUENCY OF THE GIVEN SIGNAL. A CONTROLLED SIGNAL GENERATOR PRODUCES THE GIVEN SIGNAL, AND THE GIVEN SIGNAL IS THEN DIVIDED DOWN TO A THIRD FREQUENCY WHEREIN THE THIRD FREQUENCY IS DESIRABLY THE LARGEST COMMON DIVISOR OF THE GIVEN SIGNAL AND THE HIGHER FREQUENCY SIGNAL. A PHASE

    DETECTOR SAMPLER COMPARES THE PHASE OF THE HIGHER FREQUENCY SIGNAL WITH THE PHASE OF THE SIGNAL AT THE THIRD FREQUENCY, AND CORRECTION IS MADE IN THE FREQUENCY OF THE GIVEN SIGNAL UNTIL THE PROPER PHASE RELATION IS ACHIEVED BETWEEN THE GIVEN SIGNAL AND THE HIGHER FREQUENCY SIGNAL.

    Master/slave clock arrangement for providing reliable clock signal
    10.
    发明授权
    Master/slave clock arrangement for providing reliable clock signal 失效
    主/从时钟布置,用于提供可靠的时钟信号

    公开(公告)号:US4025874A

    公开(公告)日:1977-05-24

    申请号:US681952

    申请日:1976-04-30

    Applicant: Duane L. Abbey

    Inventor: Duane L. Abbey

    CPC classification number: H03L7/24 H03K3/0307

    Abstract: The outputs of two like frequency oscillators are combined to form a single reliable clock signal, with one oscillator functioning as a slave under the control of the other to achieve phase coincidence when the master is operative and in a free-running mode when the master is inoperative so that failure of either oscillator produces no effect on the clock signal.

    Abstract translation: 两个类似的频率振荡器的输出被组合以形成单个可靠的时钟信号,一个振荡器在另一个控制下用作从机,以在主机工作时实现相位一致,并且当主机处于自由运行模式时 不能使任何一个振荡器的故障对时钟信号没有影响。

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