公开(公告)号：US4213156A

公开(公告)日：1980-07-15

申请号：US899273

申请日：1978-04-24

Applicant: Douglas G. Jarrett

Inventor： Douglas G. Jarrett

IPC: H04N1/36 ,  H03B3/06

CPC classification number: H04N1/36

Abstract: A source of clock pulses is coupled to a synthesizer of higher frequency pulses which comprises a frequency divider which is reset in response to each of the higher frequency pulses. A lower frequency square wave signal is applied to circuitry for generating blanking pulses and low frequency pulses to be inserted periodically between the higher frequency pulses after the blanking pulses are applied to the synthesizer.

Abstract translation: 时钟脉冲源耦合到较高频率脉冲的合成器，其包括响应于每个较高频率脉冲复位的分频器。 较低频率的方波信号被施加到用于产生消隐脉冲和低频脉冲的电路，以便在将消隐脉冲施加到合成器之后周期性地插入较高频率脉冲之间。