公开(公告)号：US06261382B1

公开(公告)日：2001-07-17

申请号：US09495795

申请日：2000-02-01

申请人： Eckhard Marx ,  Detlef Gerhard ,  Steffen Franke

发明人： Eckhard Marx ,  Detlef Gerhard ,  Steffen Franke

IPC分类号： H01L2930

CPC分类号： H01L23/544 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer marking is disclosed, which is represented by a large number of soft marks incorporated into a surface of a wafer. The soft marks each have a depth of at least 4 &mgr;m, an internal diameter of at least 50 &mgr;m and, in a particularly advantageous manner, a minimum gradient their surface of 0.2. These depressions can be proded, using appropriate technology, with depths of up to &mgr;m.

摘要翻译： 公开了一种晶片标记，其由并入晶片表面的大量软标记表示。 软标记各自具有至少4μm的深度，至少50μm的内径，并且以特别有利的方式，其表面为0.2的最小梯度。 这些凹陷可以使用适当的技术，深度达到妈妈。

公开(公告)号：US06465871B2

公开(公告)日：2002-10-15

申请号：US09853775

申请日：2001-05-14

申请人： Tadaharu Minato

发明人： Tadaharu Minato

IPC分类号： H01L2930

CPC分类号： H01L29/7392 ,  H01L21/263 ,  H01L29/32

摘要： A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semiconductor switching device can be improved without causing any unacceptable disadvantages for other characteristics.

摘要翻译： 主电流通过的半导体层的结构使得半导体层中的载流子寿命根据载体寿命的预定分布不均匀。 因此，可以提高半导体开关器件的截止特性，而不会对其他特性造成任何不可接受的缺点。

公开(公告)号：US06593641B1

公开(公告)日：2003-07-15

申请号：US09906550

申请日：2001-07-16

申请人： Eugene A. Fitzergald

发明人： Eugene A. Fitzergald

IPC分类号： H01L2930

CPC分类号： H01L29/802 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66893 ,  H01L29/66916 ,  H01L29/7838

摘要： Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

公开(公告)号：US06420775B1

公开(公告)日：2002-07-16

申请号：US08806985

申请日：1997-02-26

申请人： Shuji Asai

发明人： Shuji Asai

IPC分类号： H01L2930

CPC分类号： H01L29/812 ,  H01L29/32 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A compound semiconductor device having improved backgate voltage resistance characteristics. To improve the backgate voltage resistance of a compound semiconductor device having field effect transistors on a main surface of a semi-insulating substrate, boron ions are implanted on the rear surface to form a defect-rich layer having carrier recombination centers.

摘要翻译： 具有改进的背栅电压电阻特性的复合半导体器件。 为了提高在半绝缘基板的主面上具有场效应晶体管的复合半导体器件的背栅电压，在背面注入硼离子，形成具有载流子复合中心的缺陷丰富层。

公开(公告)号：US06475897B1

公开(公告)日：2002-11-05

申请号：US09639709

申请日：2000-08-14

申请人： Takashi Hosaka

发明人： Takashi Hosaka

IPC分类号： H01L2930

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/013

摘要： A semiconductor device, such as an IC package, having the same size as an IC chip and having improved qualities is manufactured at a low cost by a particular manufacturing method. The semiconductor device has stepped-projection bumps bonded to electrode pads on a semiconductor substrate in which a semiconductor element is formed. A column portion and a portion in a horizontal portion of each stepped-projection bump are exposed while the other portion of the bump is covered with a protective material. When windows of the protective material corresponding to the column portions are formed, the windows are patterned by using a masking material based on a photoetching method, and the protective material is removed by etching.

摘要翻译： 通过特定的制造方法以低成本制造具有与IC芯片相同尺寸并且具有改进的品质的诸如IC封装的半导体器件。 半导体器件具有接合到其中形成半导体元件的半导体衬底上的电极焊盘的阶梯式凸起凸块。 每个阶梯式凸起凸起的柱部分和水平部分中的一部分被暴露，而凸块的另一部分被保护材料覆盖。 当形成对应于柱部分的保护材料的窗口时，通过使用基于光刻方法的掩模材料对窗口进行图案化，并且通过蚀刻去除保护材料。

公开(公告)号：US06222253B1

公开(公告)日：2001-04-24

申请号：US09531628

申请日：2000-03-21

申请人： Devendra Kumar Sadana ,  Orin Wayne Holland

发明人： Devendra Kumar Sadana ,  Orin Wayne Holland

IPC分类号： H01L2930

CPC分类号： H01L21/76243

摘要： A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200° C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

摘要翻译： 描述了一种用于形成上绝缘体的工艺，其包括以下步骤：在升高的温度下将氧离子注入到硅衬底中，以较低的剂量离子注入低于200℃的氧气以形成非晶硅层;以及 退火步骤以单独形成有缺陷的单晶硅和多晶硅或多晶硅的混合物，然后形成来自非晶硅层的氧化硅，以在硅衬底的表面下方形成连续的氧化硅层，以提供分离的表面硅层。 本发明克服了形成不连续掩埋氧化层的氧化硅的孤立孤岛的问题。

公开(公告)号：US06222252B1

公开(公告)日：2001-04-24

申请号：US09069146

申请日：1998-04-29

申请人： Masanori Numano ,  Moriya Miyashita

发明人： Masanori Numano ,  Moriya Miyashita

IPC分类号： H01L2930

CPC分类号： C30B29/06 ,  C30B15/00 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/10844 ,  H01L29/32 ,  Y10S257/913

摘要： A semiconductor substrate is provided which can efficiently exhibit intrinsic gettering (IG) effect, is less likely to cause slipping or dislocation, and causes no significant lowering in mechanical strength. The semiconductor substrate has bulk micro defects dispersed at a density of not less than 1011 micro defects/cm3 in the interior thereof.

摘要翻译： 提供能够有效地显示固有吸气（IG）效应的半导体衬底，不太可能引起滑脱或错位，并且不会显着降低机械强度。 半导体衬底具有在其内部以不小于1011微缺陷/ cm3的密度分散的大量微缺陷。

公开(公告)号：US06831350B1

公开(公告)日：2004-12-14

申请号：US10677844

申请日：2003-10-02

申请人： Chun-Li Liu ,  Alexander L. Barr ,  John M. Grant ,  Bich-Yen Nguyen ,  Marius K. Orlowski ,  Tab A. Stephens ,  Ted R. White ,  Shawn G. Thomas

发明人： Chun-Li Liu ,  Alexander L. Barr ,  John M. Grant ,  Bich-Yen Nguyen ,  Marius K. Orlowski ,  Tab A. Stephens ,  Ted R. White ,  Shawn G. Thomas

IPC分类号： H01L2930

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/04 ,  H01L29/665 ,  H01L29/7833

摘要： A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.

摘要翻译： 半导体结构包括具有第一晶格常数的第一松弛半导体材料的衬底。 半导体器件层覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料。 此外，介电层介于基板和半导体器件层之间，其中介电层包括设置在电介质层内的编程过渡区，用于在第一晶格常数和第二晶格常数之间转变。 编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度 不超过第二临界厚度。 多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。 还公开了制备该方法的方法。

公开(公告)号：US06478883B1

公开(公告)日：2002-11-12

申请号：US09529661

申请日：2000-04-18

申请人： Masaro Tamatsuka ,  Ken Aihara ,  Katsuhiko Miki ,  Hiroshi Takeno ,  Yoshinori Hayamizu

发明人： Masaro Tamatsuka ,  Ken Aihara ,  Katsuhiko Miki ,  Hiroshi Takeno ,  Yoshinori Hayamizu

IPC分类号： H01L2930

CPC分类号： C30B29/06 ,  C30B15/00 ,  H01L21/3225

摘要： A silicon wafer for epitaxial growth consisting of a highly boron-doped silicon single crystal wafer, an antimony-doped silicon single crystal wafer or a phosphorus-doped silicon single crystal wafer, which allows easy oxygen precipitation and exhibits high gettering ability in spite of its suppressed oxygen concentration, and an epitaxial silicon wafer in which an epitaxial layer grown by using the aforementioned wafer as a substrate wafer has an extremely low heavy metal impurity concentration are produced with high productivity and supplied. The present invention relates to a boron-doped silicon single crystal wafer having a resistivity of from 10 m&OHgr;·cm to 100 m&OHgr;·cm, an antimony-doped silicon single crystal wafer, or a phosphorus-doped silicon single crystal wafer, which are produced by slicing a silicon single crystal ingot grown by the Czochralski method with nitrogen doping. The present invention also relates to an epitaxial wafer, wherein an epitaxial layer is formed on a surface of the aforementioned wafers. The present invention further relates to method for producing them.

摘要翻译： 用于外延生长的硅晶片由高掺硼硅单晶晶片，锑掺杂硅单晶晶片或磷掺杂硅单晶晶片组成，其允许容易的氧沉淀并且表现出高的吸杂能力 抑制氧浓度，并且以高生产率生产其中通过使用上述晶片生长的外延层作为基板晶片具有极低重金属杂质浓度的外延硅晶片。 本发明涉及电阻率为10mOMEGA.cm至100mOMEGA.cm的硼掺杂硅单晶晶片，掺锑硅单晶晶片或磷掺杂硅单晶晶片，其生产 通过用氮掺杂切片通过Czochralski法生长的硅单晶锭。 本发明还涉及外延晶片，其中在上述晶片的表面上形成外延层。 本发明还涉及它们的制造方法。

公开(公告)号：US06361619B1

公开(公告)日：2002-03-26

申请号：US09385108

申请日：1999-08-27

申请人： Robert J. Falster ,  Martin Jeffrey Binns ,  Harold W. Korb

发明人： Robert J. Falster ,  Martin Jeffrey Binns ,  Harold W. Korb

IPC分类号： H01L2930

CPC分类号： H01L21/3225

摘要： A process for heat-treating a single crystal silicon wafer to dissolve agglomerated vacancy defects and to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a thermal anneal to dissolve agglomerated vacancy defects present in a stratum extending from the front surface toward the center of the wafer. The annealed wafer is then heat-treated to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The heat-treated wafer is cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.

摘要翻译： 公开了一种用于在随后的热处理步骤中热处理单晶硅晶片以溶解聚集的空位缺陷并影响晶片中氧的析出行为的方法。 该晶片具有前表面，后表面和在前表面和后表面之间的中心平面。 在该过程中，对晶片进行热退火以溶解存在于从表面朝向晶片中心延伸的层中的附聚空位缺陷。 然后对经退火的晶片进行热处理以形成晶格空位，空位在大部分硅中形成。 热处理的晶片从所述热处理的温度以允许一些但不是全部晶格空位扩散到前表面的速率冷却，以产生具有空位浓度分布的晶片，其中峰密度 处于或接近中心平面，其浓度通常在晶片前表面的方向上减小。