公开(公告)号：US06621146B1

公开(公告)日：2003-09-16

申请号：US09964157

申请日：2001-09-26

申请人： Robert J. Bowman

发明人： Robert J. Bowman

IPC分类号： H01L29167

CPC分类号： H01L27/0738 ,  H01L21/823418 ,  H01L29/7835 ,  H01L29/8605

摘要： An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.

摘要翻译： 集成电路包括衬底和退化晶体管。 退化晶体管包括形成在衬底上的控制端子，形成在第一控制端子下方的衬底中的沟道，在通道的相对侧上嵌入衬底中的第一和第二重掺杂区域，位于第一控制端子上的第一和第二输出触点 第一和第二重掺杂区域以及在第一重掺杂区域和沟道之间延伸的轻掺杂区域。 轻掺杂区域具有选择的长度，使得第一输出触点与控制端子的相应边缘间隔开至少两倍于为其中集成电路的技术所限定的最小距离的距离 并且轻掺杂区域具有与第一输出触点串联的期望电阻。

公开(公告)号：US06198157B1

公开(公告)日：2001-03-06

申请号：US09024661

申请日：1998-02-17

申请人： Hidetsugu Ishida ,  Seiichi Isomae

发明人： Hidetsugu Ishida ,  Seiichi Isomae

IPC分类号： H01L29167

CPC分类号： H01L29/167 ,  H01L21/26506 ,  H01L21/3221 ,  H01L29/161 ,  Y10S257/913 ,  Y10S257/914

摘要： To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.

摘要翻译： 为了通过离子注入硼来提高吸杂性能，通过使用质量好的外延晶片，可以提高半导体器件的制造成本，从而抑制位错的发生。为此，形成外延层，其中形成约1μm的外延层 提供注入硼离子的CZ半导体衬底，其是掺杂剂和不是掺杂剂的碳离子，并且在外延层的表面上形成晶体管。

公开(公告)号：US06794731B2

公开(公告)日：2004-09-21

申请号：US09169218

申请日：1998-10-09

申请人： Stephen A. Stockman ,  Daniel A. Steigerwald ,  Changhua Chen

发明人： Stephen A. Stockman ,  Daniel A. Steigerwald ,  Changhua Chen

IPC分类号： H01L29167

CPC分类号： H01L33/305 ,  H01L29/207 ,  H01S5/305 ,  Y10S257/918

摘要： A method for improving the operating stability of compound semiconductor minority carrier devices and the devices created using this method are described. The method describes intentional introduction of impurities into the layers adjacent to the active region, which impurities act as a barrier to the degradation process, particularly undesired defect formation and propagation. A preferred embodiment of the present invention uses O doping of III-V optoelectronic devices during an epitaxial growth process to improve the operating reliability of the devices.

摘要翻译： 描述了一种用于提高化合物半导体少数载流子器件的操作稳定性的方法以及使用该方法制造的器件。 该方法描述了有意将杂质引入邻近有源区的层中，杂质作为降解过程的障碍，特别是不期望的缺陷形成和传播。 本发明的优选实施例在外延生长过程中使用III-V光电子器件的O掺杂来提高器件的工作可靠性。

公开(公告)号：US06552414B1

公开(公告)日：2003-04-22

申请号：US09331932

申请日：1999-08-27

申请人： Jörg Horzel ,  Jozef Szlufcik ,  Mia Honoré ,  Johan Nijs

发明人： Jörg Horzel ,  Jozef Szlufcik ,  Mia Honoré ,  Johan Nijs

IPC分类号： H01L29167

CPC分类号： H01L21/67115 ,  H01L21/67109 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/0684 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) without having etched said second diffusion region (15) substantially.

摘要翻译： 本发明描述了一种制造半导体器件的方法，包括半导体衬底（2），其形状为切片，该方法包括以下步骤：步骤1）选择性地将基于固体的掺杂剂源的图案施加到第一 所述半导体衬底（2）的主表面; 步骤2）通过在围绕所述半导体衬底（2）的气态环境中的受控热处理步骤将掺杂剂原子从所述基于固体的掺杂剂源扩散到所述衬底（2）中，所述基于固体的掺杂剂源扩散 直接进入所述衬底（2）以形成第一扩散区（12），并且此时将所述掺杂剂从所述固体基掺杂剂源经由所述气态环境间接扩散到所述衬底（2）中以形成第二扩散区（ 15）在所述衬底（2）的至少一些未被所述图案覆盖的区域中; 和步骤3）形成基本上与所述第一扩散区域（12）对准的金属接触图案（20），而没有基本上蚀刻所述第二扩散区域（15）。

公开(公告)号：US06627973B1

公开(公告)日：2003-09-30

申请号：US10244129

申请日：2002-09-13

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

IPC分类号： H01L29167

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

公开(公告)号：US06548886B1

公开(公告)日：2003-04-15

申请号：US09508467

申请日：2000-03-10

申请人： Atsushi Ikari ,  Masami Hasebe ,  Katsuhiko Nakai ,  Hikaru Sakamoto ,  Wataru Ohashi ,  Taizo Hoshino ,  Toshio Iwasaki

发明人： Atsushi Ikari ,  Masami Hasebe ,  Katsuhiko Nakai ,  Hikaru Sakamoto ,  Wataru Ohashi ,  Taizo Hoshino ,  Toshio Iwasaki

IPC分类号： H01L29167

CPC分类号： C30B29/06 ,  C30B15/203 ,  C30B15/206 ,  H01L21/3225

摘要： A silicon semiconductor substrate is obtained by deriving a silicon semiconductor substrate from a silicon single crystal grown by the Czochralski method from a molten silicon containing not less than 1×1016 atoms/cm3 and not more than 1.5×1019 atoms/cm3 of nitrogen and heat-treating the silicon semiconductor substrate at a temperature of not less than 1000° C. and not more than 1300° C. for not less than one hour and is characterized by the fact that the density of crystal defects measuring not less than 0.1 &mgr;m as reduced to diameter is not more than 104 pieces/cm3 at least in the region reaching a depth of 1 &mgr;m from the surface of the substrate and the nitrogen content at the center of thickness of the silicon semiconductor substrate is not less than 1×1013 atoms/cm3 and not more than 1×1016 atoms/cm3.

摘要翻译： 通过从由Czochralski法生长的硅单晶从含有不小于1×10 16原子/ cm 3且不大于1.5×10 19原子/ cm 3的氮的熔融硅衍生硅半导体衬底而获得硅半导体衬底，并热处理 硅半导体基板在不低于1000℃且不超过1300℃的温度下不低于1小时，其特征在于，测量不小于0.1μm的直径的晶体缺陷的密度减小到直径 至少在从衬底的表面到达1um深度的区域中，不超过104个/ cm 3，并且硅半导体衬底的厚度中心处的氮含量不小于1×10 13原子/ cm 3，而不是更多 比1×1016原子/ cm3。

公开(公告)号：US06469368B2

公开(公告)日：2002-10-22

申请号：US09897027

申请日：2001-07-03

申请人： Norbert Galster

发明人： Norbert Galster

IPC分类号： H01L29167

CPC分类号： H01L29/66136 ,  H01L21/263 ,  H01L29/861 ,  Y02P70/605

摘要： In a method for producing a high-speed power diode with soft recovery, in which method the carrier life within the associated semiconductor substrate (10) is governed by first, unmasked bombardment (14) with an axial profile and by subsequent, second, masked bombardment (15) with a lateral profile, improved reverse characteristics are achieved in that the first, unmasked bombardment is ion bombardment (14) which governs the switching response of the power diode and in that the second, masked bombardment is electron bombardment (15), which reduces the active area of the power diode. In a power diode equipped with such a semiconductor substrate (10), the thermal resistance Rth is reduced in relation to the active area of the power diode.

摘要翻译： 在用于制造具有软恢复的高速功率二极管的方法中，在该方法中，相关联的半导体衬底（10）内的载体寿命由具有轴向轮廓的第一未被掩蔽的轰击（14）和随后的第二掩模 实现了具有横向轮廓的轰击（15），改进了反向特性，因为第一次未掩蔽的轰击是控制功率二极管的开关响应的离子轰击（14），并且第二个被掩蔽的轰击是电子轰击（15） ，这降低了功率二极管的有效面积。 在配备有这种半导体基板（10）的功率二极管中，热电阻Rth相对于功率二极管的有效面积减小。

公开(公告)号：US06750532B2

公开(公告)日：2004-06-15

申请号：US10336604

申请日：2003-01-03

申请人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

发明人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

IPC分类号： H01L29167

CPC分类号： H01L21/2807 ,  H01L21/823842

摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.

摘要翻译： 在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个 一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同 与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。 与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。 例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分中的Ge浓度低于10 ％。

公开(公告)号：US06635950B1

公开(公告)日：2003-10-21

申请号：US09665616

申请日：2000-09-19

申请人： Hidetsugu Ishida ,  Seiichi Isomae

发明人： Hidetsugu Ishida ,  Seiichi Isomae

IPC分类号： H01L29167

CPC分类号： H01L29/167 ,  H01L21/26506 ,  H01L21/3221 ,  H01L29/161 ,  Y10S257/913 ,  Y10S257/914

摘要： To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.

摘要翻译： 为了通过离子注入硼来提高吸杂性能，通过使用质量好的外延晶片，可以提高半导体器件的制造成本，从而抑制位错的发生。为此，形成外延层，其中形成约1μm的外延层 提供注入硼离子的CZ半导体衬底，其是掺杂剂和不是掺杂剂的碳离子，并且在外延层的表面上形成晶体管。

公开(公告)号：US06329704B1

公开(公告)日：2001-12-11

申请号：US09458530

申请日：1999-12-09

申请人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

发明人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

IPC分类号： H01L29167

CPC分类号： H01L21/2652 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/6659

摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

摘要翻译： 一种用于在硅衬底内形成超浅结深度掺杂区的工艺。 该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。 植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。 使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。 使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。 由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。