公开(公告)号：US06559528B2

公开(公告)日：2003-05-06

申请号：US09785503

申请日：2001-02-20

申请人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

发明人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

IPC分类号： H01L23498

CPC分类号： H01L24/97 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49872 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.

摘要翻译： 公开了一种半导体器件10，其包括具有第一元件电极12的布置的第一半导体元件11，具有第二元件电极14的布置的第二半导体元件13，将第一元件电极的部分12b电连接在一起的连接构件15 12和第二元件电极14，覆盖第一半导体元件11的主表面11a和第二半导体元件13的背面13b的绝缘层17，形成在绝缘层17上并电连接到第二半导体元件13的布线层22的布线层22。 露出在开口部分21中的第一元件电极部分12b和作为布线层22的一部分形成在绝缘层17上的外部电极23。

公开(公告)号：US06576993B2

公开(公告)日：2003-06-10

申请号：US10045825

申请日：2001-10-19

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L23498

CPC分类号： H01L24/06 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

摘要翻译： 用于形成基本上芯片级封装和所得结构的方法。 所述方法包括在半导体芯片的有源表面上施加粘合剂以在有源表面的一部分上形成图案化的粘合剂层。 提供具有内引线端和外引线端的引线架。 引线的内引线端靠近无粘合剂区域排列，并且引线连接到半导体芯片的有源表面上的粘合剂层。 外部引线端部被定向以形成基本上不大于半导体芯片的尺寸的覆盖区域。

公开(公告)号：US06521981B2

公开(公告)日：2003-02-18

申请号：US09765376

申请日：2001-01-22

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

IPC分类号： H01L23498

CPC分类号： H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/50 ,  H01L2224/73215 ,  H01L2224/85951 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/20753 ,  H01L2224/05599

摘要： A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

公开(公告)号：US06288443B1

公开(公告)日：2001-09-11

申请号：US09319393

申请日：1999-06-02

申请人： David Finn ,  Manfred Rietzler

发明人： David Finn ,  Manfred Rietzler

IPC分类号： H01L23498

CPC分类号： H01L24/83 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

摘要： A chip module (37) includes a substrate (12) and at least one chip (38) arranged on the substrate, wherein the chip 5 (11) is contacted via its terminal surfaces onto connecting leads (14, 15) of the substrate (12) and has a thickness d which is reduced compared to its original thickness D as a result of a removal of material on its rear side (39).

摘要翻译： 芯片模块（37）包括基板（12）和布置在基板上的至少一个芯片（38），其中芯片5（11）经由其端子表面接触到基板的连接引线（14,15） 12），并且具有与其原始厚度D相比减小的厚度d，作为其后侧（39）上的材料的移除的结果。