公开(公告)号：US08368071B2

公开(公告)日：2013-02-05

申请号：US11716068

申请日：2007-03-09

Applicant: Akira Ishikawa

Inventor： Akira Ishikawa

IPC: H01L29/04

CPC classification number: H01L29/786 ,  G02F1/136213 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L29/4908 ,  H01L29/78648 ,  Y10S257/903 ,  Y10S257/906 ,  Y10S257/908 ,  Y10S257/924

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract translation: 在具有薄膜晶体管和保持电容的半导体器件中形成源电极和漏电极时由于应力引起的半导体膜，电容电极等的裂纹的半导体器件及其制造方法 提供三个或更多个电容电极。 在形成源电极和漏电极之前，形成用于缓和应力的晶体硅膜，然后打开与薄膜晶体管的半导体膜连接的接触孔，并将作为源电极和漏极的金属膜 形成电极。

公开(公告)号：US07763924B2

公开(公告)日：2010-07-27

申请号：US12244747

申请日：2008-10-02

Applicant: Wen-Kuei Huang

Inventor： Wen-Kuei Huang

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10855 ,  H01L27/10835 ,  H01L27/1085 ,  H01L27/10867 ,  Y10S257/906 ,  Y10S257/908

Abstract: A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.

Abstract translation: 动态随机存取存储器结构包括设置在衬底中的凹入栅极晶体管; 沟槽电容器结构，其设置在所述基板中并电连接到所述凹陷栅极晶体管的第一源极/漏极; 设置在所述沟槽电容器结构上并与所述沟槽电容器结构接触的第一导电结构; 布置在第一导电结构上并与第一导电结构接触的堆叠电容器结构，其中沟槽电容器结构的底部电极和堆叠电容器结构的顶部电极电连接以用作公共电极; 以及设置在所述凹入栅极晶体管的第二源极/漏极上方并电连接到所述第二源极/漏极的位线，其中所述位线的顶部低于所述凹入栅极晶体管的栅极导电层的顶部 。

公开(公告)号：US07745279B2

公开(公告)日：2010-06-29

申请号：US11331703

申请日：2006-01-13

Applicant: Yee-Chia Yeo ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/8242

CPC classification number: H01L27/0805 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/65 ,  H01L29/66181 ,  H01L29/94 ,  Y10S257/905 ,  Y10S257/908

Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Abstract translation: 在包括硅表面层的半导体衬底上形成去耦电容器。 在半导体表面层的一部分中形成基本平坦的底部电极。 电容器电介质覆盖在底部电极上。 电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。 在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

公开(公告)号：US07649259B2

公开(公告)日：2010-01-19

申请号：US11316887

申请日：2005-12-27

Applicant: Mizuki Ono ,  Yuichi Motoi

Inventor： Mizuki Ono ,  Yuichi Motoi

IPC: H01L23/52

CPC classification number: H01L27/101 ,  H01L27/105 ,  Y10S257/905 ,  Y10S257/908

Abstract: A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the second wiring line group being arranged in parallel with each other and being movable in the vicinity of each intersection with the wiring lines of the first wiring line group, and a plurality of metal regions which are formed to be joined with the wiring lines constituting the second wiring line group, and have a work function different from that of the metal forming the first wiring line group.

Abstract translation: 半导体器件包括由金属构成的第一布线线组，第一布线线组的布线彼此平行布置，第二布线线组由半导体制成并与第一布线组交叉，布线 第二布线线组的线相互平行配置，并且能够在与第一布线线组的布线相交的各交点附近移动，并且形成为与布线接合的多个金属区 构成第二配线组，并且具有与形成第一配线组的金属不同的功函数。

公开(公告)号：US07521763B2

公开(公告)日：2009-04-21

申请号：US11619357

申请日：2007-01-03

Applicant: Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

Inventor： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L31/00 ,  H01L29/00 ,  H01L23/34

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.

Abstract translation: 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

公开(公告)号：US07456459B2

公开(公告)日：2008-11-25

申请号：US11516377

申请日：2006-09-06

Applicant: Lixi Wan

Inventor： Lixi Wan

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/04 ,  H01L29/12 ,  H01L31/036 ,  H01L31/112 ,  H01L29/786 ,  H01L29/80 ,  H01L29/00

CPC classification number: H05K1/162 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/908

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract translation: 本发明公开了具有通孔连接和电极的电容器，其设计成使得它们提供低电感路径，从而减少所需的电容，同时能够使用嵌入式电容器进行功率输送和其它用途。 本发明的一个实施例公开了一种电容器，包括：顶部电容器电极和底部电容器电极，其中顶部电极小于底部电极，包括在电容器的所有侧面上; 在阵列中，位于顶部和底部电容器电极的所有侧面上的多个通孔，其中顶部电极和连接到顶部电极的通孔用作内部导体，并且底部电极和连接到底部电极的通孔 作为外部导体。

公开(公告)号：US07247902B2

公开(公告)日：2007-07-24

申请号：US11122720

申请日：2005-05-05

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L27/108

CPC classification number: H01L27/10817 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

Abstract: A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal wiring layer are sequentially connected. Within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.

Abstract translation: 半导体器件包括第一金属层，其包括连接到衬底内的扩散层的掩埋金属层或下层布线。 依次连接第一金属布线层，具有掩埋金属层的第二金属层和第二金属布线层。 在穿过绝缘层的沟槽中，从绝缘层的上方和下方以及绝缘层之一夹着金属布线层，形成电容元件C.

公开(公告)号：US20070023812A1

公开(公告)日：2007-02-01

申请号：US11541726

申请日：2006-10-03

Applicant: Shinichiroh Ikemasu ,  Narumi Okawa

Inventor： Shinichiroh Ikemasu ,  Narumi Okawa

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  Y10S257/905 ,  Y10S257/908

Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.

公开(公告)号：US07135731B2

公开(公告)日：2006-11-14

申请号：US10707396

申请日：2003-12-10

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract translation: 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。

公开(公告)号：US07126154B2

公开(公告)日：2006-10-24

申请号：US10933497

申请日：2004-09-03

Applicant: Valentine Rosskopf ,  Susanne Lachenmann ,  Sibina Sukman-Prähofer ,  Andreas Felber

Inventor： Valentine Rosskopf ,  Susanne Lachenmann ,  Sibina Sukman-Prähofer ,  Andreas Felber

IPC: H01L23/58 ,  H01L29/10 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L27/10873 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5002 ,  H01L22/34 ,  H01L2924/0002 ,  Y10S257/905 ,  Y10S257/908 ,  H01L2924/00

Abstract: A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.

Abstract translation: 用于确定基于单面掩埋带概念构造的矩阵状单元阵列中的存储单元的电特性的测试结构具有在两个相邻存储单元中的存储电容器中的内部电极之间的连接 该行的有源区为了产生串联电路。 第一存储单元中的第一选择晶体管和第一存储电容器以及第二存储单元中的第二选择晶体管和第二存储电容器，第一和第二选择晶体管的有源区不连接在第一和第二选择晶体管之间 通过接触式位线。