公开(公告)号：US06965139B2

公开(公告)日：2005-11-15

申请号：US09572466

申请日：2000-05-17

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L21/8242 ,  H01L21/82 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10817 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.When manufacturing the semiconductor device, the second layer-insulating layer is formed in such a way as to cover the metal wiring layer on the first layer-insulating layer. Removal is performed of at least respective parts, corresponding to a memory cell portion, of the first and the second layer-insulating layers. Thereafter, the capacitive element C is formed in regions corresponding to the removed portions of the first and the second layer-insulating layer.As a result of this, the invention provides a semiconductor device and a method of manufacturing the same, which, in the semiconductor device having co-loaded a semiconductor memory and a logic circuit on the same semiconductor substrate, enables realizing both the increase in the capacity of the semiconductor memory and the increase in the degree of integration of the logic circuit.

Abstract translation: 半导体器件具有以下结构。 由掩埋金属层构成的第一金属层连接到衬底内的扩散层或下层布线。 此外，依次连接第一金属布线层，由埋入金属层构成的第二金属层和第二金属布线层。 并且在通过绝缘层的沟槽内，从金属布线层的上下夹着金属布线层以及其中一个绝缘层，形成电容元件C.在制造半导体器件时，形成第二层绝缘层 以覆盖第一层绝缘层上的金属布线层的方式。 至少对应于第一和第二层绝缘层的存储单元部分的相应部分进行去除。 此后，电容元件C形成在与第一和第二层绝缘层的去除部分对应的区域中。 结果，本发明提供了一种半导体器件及其制造方法，其在同一半导体衬底上共同加载半导体存储器和逻辑电路的半导体器件中，能够实现两者的增加 半导体存储器的容量和逻辑电路的集成程度的增加。

公开(公告)号：US06642101B2

公开(公告)日：2003-11-04

申请号：US10289411

申请日：2002-11-07

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L218242

CPC classification number: H01L27/10855 ,  H01L21/76816 ,  H01L27/10814 ,  H01L28/91

Abstract: A semiconductor memory device having a high quality storage node electrode preventing for example connection failure between a contact plug and the storage node electrode, including first insulating films formed on a substrate, storage node contact holes formed in the first insulating films, storage node contact plugs buried in the storage node contact holes, a storage node electrode formed connected to the storage node contact plug, and a second insulating film formed above the first insulating film at a gap of the storage node electrode, the storage node electrode and the storage node contact plug being connected at least at part of the top surface and the side surface of the storage node contact plug or the storage node electrode and the second inter-layer insulating film being in contact at least at part of the top surface and the side surface of the second insulating film, and a method for producing the same.

公开(公告)号：US20050205914A1

公开(公告)日：2005-09-22

申请号：US11122720

申请日：2005-05-05

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L21/8242 ,  H01L21/82 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10817 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C. When manufacturing the semiconductor device, the second layer-insulating layer is formed in such a way as to cover the metal wiring layer on the first layer-insulating layer. Removal is performed of at least respective parts, corresponding to a memory cell portion, of the first and the second layer-insulating layers. Thereafter, the capacitive element C is formed in regions corresponding to the removed portions of the first and the second layer-insulating layer. As a result of this, the invention provides a semiconductor device and a method of manufacturing the same, which, in the semiconductor device having co-loaded a semiconductor memory and a logic circuit on the same semiconductor substrate, enables realizing both the increase in the capacity of the semiconductor memory and the increase in the degree of integration of the logic circuit.

Abstract translation: 半导体器件具有以下结构。 由掩埋金属层构成的第一金属层连接到衬底内的扩散层或下层布线。 此外，依次连接第一金属布线层，由埋入金属层构成的第二金属层和第二金属布线层。 并且在通过绝缘层的沟槽内，从金属布线层的上下夹着金属布线层以及其中一个绝缘层，形成电容元件C.在制造半导体器件时，形成第二层绝缘层 以覆盖第一层绝缘层上的金属布线层的方式。 至少对应于第一和第二层绝缘层的存储单元部分的相应部分进行去除。 此后，电容元件C形成在与第一和第二层绝缘层的去除部分对应的区域中。 结果，本发明提供了一种半导体器件及其制造方法，其在同一半导体衬底上共同加载半导体存储器和逻辑电路的半导体器件中，能够实现两者的增加 半导体存储器的容量和逻辑电路的集成程度的增加。

公开(公告)号：US6051462A

公开(公告)日：2000-04-18

申请号：US129086

申请日：1998-08-05

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10844 ,  H01L27/10873

Abstract: The invention relates to a process for producing a semiconductor device comprising the following steps. A first insulating film and a second insulating film are formed along a shape of the gate electrode on the logic region of the semiconductor substrate. A contact hole is formed in the first and second insulating films in the cell region, and a side wall comprising a material preventing its own silicidation is formed on the inner wall thereof. A conductive material is embedded in the contact hole through a side wall to form a plug, and then the second insulating film is removed to expose the plug and the first insulating film. A spacer side wall is formed on the side wall of the gate electrode in the logic region, and the surface of the semiconductor substrate is exposed, followed by forming a silicide layer thereon. A first interlayer insulating film is formed on the semiconductor substrate, so as to flatten the surface and the upper surface of the plug is exposed.

Abstract translation: 本发明涉及一种制造半导体器件的方法，包括以下步骤。 沿着半导体衬底的逻辑区域上的栅电极的形状形成第一绝缘膜和第二绝缘膜。 在单元区域中的第一绝缘膜和第二绝缘膜中形成接触孔，并且在其内壁上形成包含防止其自身硅化物的侧壁。 导电材料通过侧壁嵌入接触孔中以形成插头，然后去除第二绝缘膜以露出插头和第一绝缘膜。 在逻辑区域中的栅电极的侧壁上形成间隔物侧壁，并且暴露半导体衬底的表面，然后在其上形成硅化物层。 在半导体基板上形成第一层间绝缘膜，以使表面变平且露出插头的上表面。

公开(公告)号：US07247902B2

公开(公告)日：2007-07-24

申请号：US11122720

申请日：2005-05-05

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L27/108

CPC classification number: H01L27/10817 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

Abstract: A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal wiring layer are sequentially connected. Within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.

Abstract translation: 半导体器件包括第一金属层，其包括连接到衬底内的扩散层的掩埋金属层或下层布线。 依次连接第一金属布线层，具有掩埋金属层的第二金属层和第二金属布线层。 在穿过绝缘层的沟槽中，从绝缘层的上方和下方以及绝缘层之一夹着金属布线层，形成电容元件C.

公开(公告)号：US06518130B1

公开(公告)日：2003-02-11

申请号：US09672876

申请日：2000-09-29

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L218234

CPC classification number: H01L27/10894 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/10873

Abstract: A semiconductor device comprising a plurality of first transistors formed in a first region of a semiconductor substrate and a plurality of second transistors formed in a second region of the semiconductor substrate, wherein each of the first and second transistors has a gate electrode, a channel-forming region and source/drain regions; the gate electrodes constituting the first and second transistors are formed of a polysilicon layer containing an impurity and a silicide layer formed thereon; a silicide layer is formed in the source/drain regions constituting the first transistor; and no silicide layer is formed in the source/drain regions constituting the second transistor.

Abstract translation: 一种半导体器件，包括形成在半导体衬底的第一区域中的多个第一晶体管和形成在所述半导体衬底的第二区域中的多个第二晶体管，其中所述第一和第二晶体管中的每一个具有栅电极， 形成区域和源极/漏极区域; 构成第一和第二晶体管的栅电极由形成在其上的杂质和硅化物层的多晶硅层形成; 在构成第一晶体管的源/漏区中形成硅化物层; 并且在构成第二晶体管的源极/漏极区域中不形成硅化物层。

公开(公告)号：US06501119B1

公开(公告)日：2002-12-31

申请号：US09447558

申请日：1999-11-23

Applicant: Keiichi Ohno

Inventor： Keiichi Ohno

IPC: H01L27108

CPC classification number: H01L27/10855 ,  H01L21/76816 ,  H01L27/10814 ,  H01L28/91

Abstract: A semiconductor memory device having a high quality storage node electrode preventing for example connection failure between a contact plug and the storage node electrode, including first insulating films formed on a substrate, storage node contact holes formed in the first insulating films, storage node contact plugs buried in the storage node contact holes, a storage node electrode formed connected to the storage node contact plug, and a second insulating film formed above the first insulating film at a gap of the storage node electrode, the storage node electrode and the storage node contact plug being connected at least at part of the top surface and the side surface of the storage node contact plug or the storage node electrode and the second inter-layer insulating film being in contact at least at part of the top surface and the side surface of the second insulating film, and a method for producing the same.

Abstract translation: 一种半导体存储器件，其具有高质量的存储节点电极，其防止接触插塞和存储节点电极之间的连接故障，包括形成在基板上的第一绝缘膜，形成在第一绝缘膜中的存储节点接触孔，存储节点接触插塞 埋置在存储节点接触孔中，形成为与存储节点接触插塞连接的存储节点电极，以及在存储节点电极，存储节点电极和存储节点接触的间隙处形成在第一绝缘膜上方的第二绝缘膜 至少在所述存储节点接触插塞或所述存储节点电极和所述第二层间绝缘膜的顶表面和所述侧表面的至少部分上至少部分地连接插头，所述第二层间绝缘膜至少在所述顶表面和所述侧表面 第二绝缘膜及其制造方法。