公开(公告)号：US6141762A

公开(公告)日：2000-10-31

申请号：US128030

申请日：1998-08-03

Applicant: Christopher J. Nicol ,  Kanwar Jit Singh

Inventor： Christopher J. Nicol ,  Kanwar Jit Singh

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50 ,  G06F15/78 ,  G06F9/44

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/505 ,  G06F9/5094 ,  Y02B60/1217 ,  Y02B60/1285 ,  Y02B60/142 ,  Y02B60/144

Abstract: Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.

Abstract translation: 多处理器芯片的改进操作通过动态地控制芯片的处理负载并且显着地大于开/关粒度来控制这些芯片的工作电压，从而最大限度地降低整体功耗来实现。 多处理器芯片中的控制器将各个处理器的任务分配给各个处理器之间的均衡，然后控制器将芯片上的时钟频率降至尽可能低的水平，同时确保正确的运行，并最终降低电源电压 。 通过控制多处理器芯片内的各个处理元件的电源电压以及控制多处理器芯片在其中运行的系统中的其它元件的电源电压，可以进一步改进。

公开(公告)号：US6138232A

公开(公告)日：2000-10-24

申请号：US994834

申请日：1997-12-19

Applicant: Jonathan H. Shiell ,  Robert D. Marshall, Jr.

Inventor： Jonathan H. Shiell ,  Robert D. Marshall, Jr.

IPC: G06F1/32 ,  G06F1/04 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F1/08 ,  G06F9/32

CPC classification number: G06F1/32 ,  G06F1/324 ,  G06F9/30149 ,  G06F9/382 ,  G06F9/3869 ,  G06F9/4812 ,  Y02B60/1217 ,  Y02B60/144

Abstract: A microprocessor operates at a rate dependent upon the interrupt source of a plurality of interrupt sources. The rate of power consumption by the microprocessor corresponds to the selected rate of instruction operation. A rate table accessed upon receipt of an interrupt stores a table of interrupt source to rate of instruction operation. The rate table may be a read only memory or a read/write memory loaded upon initiation of the microprocessor. The rate of microprocessor instruction operation may be set by frequency of an instruction clock or by a rate of instruction dispatch. For a superscalar microprocessor the rate of instruction operation may be set by setting a number of instructions dispatched per instruction cycle. On receiving an interrupt a rate number is pushed onto a rate stack. On return from the interrupt the rate stack is popped. The microprocessor operates at a rate corresponding to the rate number at a top of the rate stack. The invention may be coordinated with system management mode power control. A predetermined system management mode rate number is pushed onto the rate stack upon receipt of a system management interrupt entering the system management mode. The rate stack is popped upon exit from system management mode to normal mode.

Abstract translation: 微处理器以取决于多个中断源的中断源的速率进行操作。 微处理器的功耗速率对应于所选择的指令操作速率。 在接收到中断时访问的速率表将中断源的表存储到指令操作速率。 速率表可以是只读存储器或在微处理器启动时加载的读/写存储器。 微处理器指令操作的速率可以由指令时钟的频率或指令发送速率来设定。 对于超标量微处理器，可以通过设置每个指令周期发送的指令数来设置指令操作速率。 在接收到中断时，速率号被推到速率堆栈上。 从中断返回时，速率堆栈弹出。 微处理器以与速率堆栈顶部的速率数相对应的速率进行操作。 本发明可以与系统管理模式功率控制协调。 在接收到进入系统管理模式的系统管理中断时，将预定的系统管理模式速率号码推送到速率堆栈。 从系统管理模式退出到正常模式时，速率堆栈弹出。

公开(公告)号：US6119241A

公开(公告)日：2000-09-12

申请号：US183342

申请日：1998-10-30

Applicant: Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

Inventor： Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3296 ,  Y02B60/1217 ,  Y02B60/1285

Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

Abstract translation: 一种处理器，通过使用包括电压，时钟和由处理器或其系统执行的操作的变量的层次来机会地优化性能。 本发明通过定义各种状态来实现性能优化，目的在于处理器执行单元正在运行时处理器处于加速电压和时钟的最佳性能状态。 状态由逻辑网络基于由温度传感器和性能控制提供的信息来选择。 逻辑网络可以设想为一个UP-DOWN计数器。 根据条件，计数器可以向上或向下进入状态“梯子”。

公开(公告)号：US6118306A

公开(公告)日：2000-09-12

申请号：US302931

申请日：1999-04-30

Applicant: John T. Orton ,  Cau L. Nguyen ,  Gurbir Singh ,  Xia Dai ,  Raviprakash Nagaraj ,  Edwin J. Pole, II

Inventor： John T. Orton ,  Cau L. Nguyen ,  Gurbir Singh ,  Xia Dai ,  Raviprakash Nagaraj ,  Edwin J. Pole, II

IPC: G01R31/30 ,  G01R23/02

CPC classification number: G06F1/324 ,  G01R31/3016 ,  G06F1/3296 ,  Y02B60/1217 ,  Y02B60/1285

Abstract: A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

Abstract translation: 一种系统包括一个组件（例如处理器），该组件包括产生以一个频率运行的内部时钟的时钟发生器。 控制器产生时钟频率变化指示并将组件置于低活动状态（例如，深度睡眠，停止授权或其他状态）。 时钟发生器由时钟频率变化指示复位，以在组件处于低活动状态时更改时钟频率。 可以选择包含不同值的存储元件来设置时钟频率。 存储元件包括熔丝组和输入引脚。

公开(公告)号：US6061803A

公开(公告)日：2000-05-09

申请号：US151938

申请日：1993-11-15

Applicant: Elie Ayache

Inventor： Elie Ayache

IPC: G06F1/08 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  Y02B60/1217

Abstract: An activity sensor monitors a microprocessor based system for a change in a logic state. In response to the change, the activity sensor provides a reset timer pulse to a delay timer circuit. The delay timer is a counter that stores a signal representation of the number of timing pulses provided by a timing clock. In response to the timer reset signal, the delay timer is reset. When the timer reset pulse is not provided for a predetermined interval, the delay timer generates a timeout pulse that causes a reduction in the frequency of a system clock.

Abstract translation: 活动传感器监视基于微处理器的系统以改变逻辑状态。 响应于该变化，活动传感器向延迟定时器电路提供复位定时器脉冲。 延迟定时器是存储由定时时钟提供的定时脉冲数的信号表示的计数器。 响应定时器复位信号，延时定时器复位。 当定时复位脉冲没有提供预定间隔时，延迟定时器产生一个超时脉冲，导致系统时钟的频率降低。

公开(公告)号：US6014751A

公开(公告)日：2000-01-11

申请号：US841858

申请日：1997-05-05

Applicant: James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

Inventor： James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

IPC: G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F1/10

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0835 ,  Y02B60/1217 ,  Y02B60/1221

Abstract: A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

Abstract translation: 描述用于操作集成在降低功耗状态的方法和装置。 该装置包括功率降低逻辑，为了将集成电路置于降低功耗状态，将集成电路中的第一组和第二组功能单元的时钟信号置于门限。 第一组功能单元的特征在于需要在集成电路内执行高速缓存一致性操作。 该装置包括输入，该输入被耦合以通过集成电路外部的另外的设备将指示存储器访问的信号接收到由集成电路可访问的存储器资源。 响应于该信号的断言，功率降低逻辑将时钟信号传播到第一组功能单元，以使得该组功能单元能够执行高速缓存一致性操作，这可能由外部存储器访问所必需 设备。

公开(公告)号：US6014051A

公开(公告)日：2000-01-11

申请号：US156889

申请日：1998-09-18

Applicant: Wendell L. Little

Inventor： Wendell L. Little

IPC: G06F1/08 ,  G06F1/32 ,  H03L1/00

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/32 ,  Y02B60/1217

Abstract: A circuit, for incorporation into an electrical system, for providing a clock signal frequency to other circuitry such as a microprocessor and/or co-processor circuitry. The clock signal frequency varies its speed depending on the available voltage and current from a host power source. The circuit maximizes clock frequency by lowering the available voltage and increasing the available supply current. The circuit can therefore provide a higher clock speed and more current for switching transistors.

Abstract translation: 一种用于结合到电气系统中的电路，用于向诸如微处理器和/或协处理器电路的其它电路提供时钟信号频率。 时钟信号频率根据主机电源的可用电压和电流而改变其速度。 该电路通过降低可用电压并增加可用的电源电流来最大化时钟频率。 因此，电路可以为开关晶体管提供更高的时钟速度和更多的电流。

公开(公告)号：US6006335A

公开(公告)日：1999-12-21

申请号：US986683

申请日：1997-12-08

Applicant: Hyeong-Sik Choi ,  Dong-Ho Lee

Inventor： Hyeong-Sik Choi ,  Dong-Ho Lee

IPC: G06F1/32 ,  G06F3/02 ,  G06F3/023 ,  G09G1/16 ,  F01B21/04

CPC classification number: G09G1/165 ,  G06F1/3203 ,  G06F3/021 ,  G06F3/0219 ,  G09G2330/021 ,  G09G2330/022 ,  Y02B60/1217

Abstract: A computer system capable of providing a visual display of a display power management signaling (DPMS) mode for user selection of different power save modes of operation. The DPMS mode is used to convert a power supply mode to a power save mode in a computer peripheral such as a monitor. The computer system includes a micro-computer installed in the monitor for determining whether the frequency of sync signals are within predetermined bands to set the power save mode, a switching element installed in the computer for controlling the power supply of a predetermined voltage under control of the micro-computer, and a luminance element installed at a predetermined location of a keyboard and powered by the operation of the switching element for providing a visual display of the DPMS mode for user selection of different power save modes of operation.

Abstract translation: 一种能够提供显示功率管理信号（DPMS）模式的视觉显示的计算机系统，用于用户选择不同的节电模式。 DPMS模式用于将计算机外围设备（如监视器）中的电源模式转换为省电模式。 计算机系统包括安装在监视器中的微型计算机，用于确定同步信号的频率是否处于预定频带内以设置省电模式;安装在计算机中的开关元件，用于控制预定电压的电源， 微型计算机以及安装在键盘的预定位置并由开关元件的操作供电的亮度元件，用于提供DPMS模式的可视显示，以供用户选择不同的省电模式。

公开(公告)号：US5987614A

公开(公告)日：1999-11-16

申请号：US877140

申请日：1997-06-17

Applicant: Phillip Merle Mitchell ,  Francisco Velasco ,  Xuyen N. Phung

Inventor： Phillip Merle Mitchell ,  Francisco Velasco ,  Xuyen N. Phung

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3259 ,  G06F1/3271 ,  G06F1/3275 ,  Y02B60/1217 ,  Y02B60/1221 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1253 ,  Y02B60/1257

Abstract: Structure and method are provided for reducing power consumption in a computer system without sacrificing computer performance or inhibiting a computer user's rapid access to the computer. An identifier, such as a device address, network address, serial number, and the like, is associated with each device or resource. Communications over a communications link such as a parallel bus, serial bus, or wireless link, are monitored by each device to determine device identifiers communicated over the link, and these identifiers are compared to the identifier associated with the monitoring device. Each device monitors the communications and is responsible for self-controlling its operating condition to minimize power consumption. Each device includes a first component which operates continuously to provide the monitoring function, and a second component that operates in a low power consumption mode unless the first component signals the second component that its operation is needed during that time period. Typically, the first component withholds a device operating input, for example a clock signal, from the second component when none of the communicated identifiers match the particular device; and provide the operating input when one matches. In the first component, the number of circuit elements is reduced so that the number of circuit elements which are continuously active are reduced. The structure and method provide very fine temporal control of power consumption in the computer system.

Abstract translation: 提供了结构和方法，用于降低计算机系统的功耗，而不会牺牲计算机性能或阻止计算机用户快速访问计算机。 诸如设备地址，网络地址，序列号等的标识符与每个设备或资源相关联。 通过诸如并行总线，串行总线或无线链路的通信链路的通信由每个设备监视以确定通过链路传送的设备标识符，并且将这些标识符与与监视设备相关联的标识符进行比较。 每个设备监控通信，并负责自我控制其运行状况，以最大限度地降低功耗。 每个设备包括连续操作以提供监视功能的第一组件，以及以低功耗模式操作的第二组件，除非第一组件在该时间段期间向第二组件通知其操作是必需的。 通常，当没有通信的标识符与特定设备匹配时，第一组件从第二组件中保留设备操作输入，例如时钟信号; 并在匹配时提供操作输入。 在第一部件中，电路元件的数量减少，使得连续有效的电路元件的数量减少。 该结构和方法提供了计算机系统功耗的非常精细的时间控制。

公开(公告)号：US5930516A

公开(公告)日：1999-07-27

申请号：US847143

申请日：1997-04-30

Applicant: LaVaughn F. Watts, Jr. ,  Steven J. Wallace

Inventor： LaVaughn F. Watts, Jr. ,  Steven J. Wallace

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  Y02B60/1217 ,  Y02B60/1275

Abstract: A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time; if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level. Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a "ready" state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation in response to the real-time sampling of CPU activity. Such adjustments are accomplished within the CPU cycles and do not affect the user's perception of performance and do not affect any system application software executing on the computer.

Abstract translation: 用于便携式计算机的实时功率节省装置和方法使用监视器来基于CPU活动级别的实时采样来确定CPU是否可以休息，并激活硬件选择器以执行监视器的确定。 如果显示器确定CPU可能休息，硬件选择器可以减少CPU时钟时间; 如果CPU处于活动状态，硬件选择器将CPU返回到之前的高速时钟电平。 在等待计算机返回到“准备就绪”状态的同时，不用用户不需要请求并且没有任何延迟的计算机的运行而发生从其休息状态的全部操作。 此外，监视器根据CPU活动的实时采样来调整计算机的性能水平以管理节能。 这些调整是在CPU周期内完成的，不会影响用户对性能的看法，也不影响在计算机上执行的任何系统应用软件。