公开(公告)号：US4126853A

公开(公告)日：1978-11-21

申请号：US833857

申请日：1977-09-16

申请人： Marvin E. Frerking

发明人： Marvin E. Frerking

IPC分类号： H03M1/00 ,  H03K13/20

CPC分类号： H03M1/84

摘要： Non-linear digital-to-analog conversion is performed by employing a plurality of counting rates and counting intervals in a digital counter to generate a variable width pulse, the width of which determines the desired analog value corresponding to the digital value to be converted.

摘要翻译： 通过在数字计数器中采用多个计数速率和计数间隔来执行非线性数模转换，以产生可变宽度脉冲，其宽度决定与要转换的数字值对应的期望模拟值。

公开(公告)号：US20240113719A1

公开(公告)日：2024-04-04

申请号：US18529134

申请日：2023-12-05

申请人： SIGMASENSE, LLC.

发明人： Phuong Huynh

IPC分类号： H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H03M1/84 ,  H03M3/00

CPC分类号： H03M1/0626 ,  H03M1/1245 ,  H03M1/462 ,  H03M1/464 ,  H03M1/84 ,  H03M3/32 ,  H03M3/43 ,  H03M3/462 ,  H03M3/476

摘要： An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).

公开(公告)号：US20150188583A1

公开(公告)日：2015-07-02

申请号：US14140801

申请日：2013-12-26

申请人： Ashoke Ravi ,  Ofir Degani ,  Hasnain Lakdawala

发明人： Ashoke Ravi ,  Ofir Degani ,  Hasnain Lakdawala

IPC分类号： H04B1/04 ,  H03M1/84

CPC分类号： H04B17/21 ,  H03F1/3241 ,  H03M1/1009 ,  H03M1/82 ,  H03M1/84 ,  H04B1/0475 ,  H04B2001/0425

摘要： This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.

摘要翻译： 本文讨论了用于补偿数字到时间转换器（DTC）的非线性的装置和方法。 在一个示例中，无线设备可以包括被配置为从基带处理器接收相位数据信息并提供用于生成无线信号的第一调制信号的数字 - 时间转换器（DTC），检测器配置为接收第一 调制信号并提供DTC的非线性指示，以及被配置为使用非线性指示向DTC提供预失真信息的预失真模块。

公开(公告)号：US5426430A

公开(公告)日：1995-06-20

申请号：US323441

申请日：1994-10-14

申请人： Eugene S. Schlig

发明人： Eugene S. Schlig

IPC分类号： G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36 ,  G11C27/02 ,  H03M1/84

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G11C27/024 ,  H03M1/84 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2320/0204 ,  G09G2320/0276 ,  G09G3/3614

摘要： A data line driver circuit having application in active matrix displays, such as thin-film transistor liquid crystal displays, uses charge metering techniques to achieve high precision and analog pipelining. Pipelining permits both the digital-analog conversion function and the presentation of the analog output to the display data line each to occupy most of the display's line time. The requirement of liquid crystals for periodic inversion of the net applied voltage is accommodated either by the circuits alone or with the display common electrode driven by a square wave.

摘要翻译： 在薄膜晶体管液晶显示器等有源矩阵显示器中应用的数据线驱动电路使用电荷计量技术来实现高精度和模拟流水线化。 流水线允许数字 - 模拟转换功能和模拟输出到显示数据线的显示，每个都占据显示器的大部分时间。 液晶对网络施加电压的周期性反转的要求由单独的电路或由方波驱动的显示公共电极来适应。

公开(公告)号：US11863197B2

公开(公告)日：2024-01-02

申请号：US18092959

申请日：2023-01-04

申请人： SigmaSense, LLC.

发明人： Phuong Huynh

IPC分类号： H03M1/06 ,  H03M1/46 ,  H03M1/12 ,  H03M3/00 ,  H03M1/84

CPC分类号： H03M1/0626 ,  H03M1/1245 ,  H03M1/462 ,  H03M1/464 ,  H03M1/84 ,  H03M3/32 ,  H03M3/43 ,  H03M3/462 ,  H03M3/476

摘要： An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).

公开(公告)号：US20230195045A1

公开(公告)日：2023-06-22

申请号：US17556457

申请日：2021-12-20

申请人： Assaf Ben-Bassat ,  Ofir Degani ,  Elan Banin ,  Shahar Gross ,  Phillip Skliar

发明人： Assaf Ben-Bassat ,  Ofir Degani ,  Elan Banin ,  Shahar Gross ,  Phillip Skliar

IPC分类号： G04F10/00 ,  H03M1/84

CPC分类号： G04F10/005 ,  H03M1/84

摘要： A method for compensating signal nonlinearities includes generating a local oscillator (LO) signal and performing phase modulation of the LO signal to generate a phase-modulated LO signal. The phase modulation is based on applying at least one digital-to-time converter (DTC) code of a plurality of DTC codes to a rising edge signal portion and a falling edge signal portion associated with the LO signal. Nonlinearities associated with the rising edge signal portion and the falling edge signal portion are determined. The at least one DTC code is adjusted based on the nonlinearities.

公开(公告)号：US3324452A

公开(公告)日：1967-06-06

申请号：US58762166

申请日：1966-10-18

申请人： GEN DYNAMICS CORP

发明人： BARRIE BRIGHTMAN ,  POMMERENING UWE A

IPC分类号： G01S1/72 ,  G10K11/34 ,  H01Q3/38 ,  H03M1/00

CPC分类号： H01Q3/385 ,  G01S1/72 ,  G10K11/346 ,  H03M1/84

公开(公告)号：US09331722B2

公开(公告)日：2016-05-03

申请号：US14140801

申请日：2013-12-26

申请人： Intel IP Corporation

发明人： Ashoke Ravi ,  Ofir Degani ,  Hasnain Lakdawala

IPC分类号： H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B1/04 ,  H03M1/84

CPC分类号： H04B17/21 ,  H03F1/3241 ,  H03M1/1009 ,  H03M1/82 ,  H03M1/84 ,  H04B1/0475 ,  H04B2001/0425

摘要： This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.

摘要翻译： 本文讨论了用于补偿数字到时间转换器（DTC）的非线性的装置和方法。 在一个示例中，无线设备可以包括被配置为从基带处理器接收相位数据信息并提供用于生成无线信号的第一调制信号的数字 - 时间转换器（DTC），检测器配置为接收第一 调制信号并提供DTC的非线性指示，以及被配置为使用非线性指示向DTC提供预失真信息的预失真模块。

公开(公告)号：US5936602A

公开(公告)日：1999-08-10

申请号：US831927

申请日：1997-04-02

申请人： Susumu Tsuchida ,  Yoshihide Nagatsu

发明人： Susumu Tsuchida ,  Yoshihide Nagatsu

IPC分类号： G02F1/133 ,  G06F1/03 ,  G09G3/20 ,  G09G3/36 ,  H03M1/84 ,  H04N5/66 ,  G09G3/28 ,  G09G5/10 ,  H04N5/57

CPC分类号： G09G3/2011 ,  G06F1/0321 ,  G09G3/3648 ,  G09G3/3662 ,  H03M1/84 ,  G09G2310/0259

摘要： In a ramp signal producing apparatus, a ramp signal is produced under low clock signal frequency in a compact circuit arrangement. Luminance control and a white balance control are carried out by the ramp signal in a liquid crystal display. The ramp signal producing apparatus is comprised of: an up/down counter for either counting up, or counting down a clock signal supplied thereto; amplitude amount converting means for converting the amplitude of the supplied clock signal into such an amplitude value corresponding to the count value of the up/down counter and for converting the amplitude value in such a manner that a change amount per one count value is increased during the count down operation by the up/down counter; and ramp signal producing means for producing such a ramp signal with an amplitude corresponding to the converted amplitude value.

摘要翻译： 在斜坡信号产生装置中，以紧凑的电路装置在低时钟信号频率下产生斜坡信号。 亮度控制和白平衡控制由液晶显示器中的斜坡信号进行。 斜坡信号产生装置包括：向上/向下计数器，用于对向其提供的时钟信号进行递增计数或递减计数; 振幅量转换装置，用于将所提供的时钟信号的幅度转换成对应于向上/向下计数器的计数值的幅度值，并且用于以每1个计数值的变化量增加的方式转换振幅值， 递减计数器的倒计时操作; 以及斜坡信号产生装置，用于产生具有对应于转换的振幅值的振幅的这种斜坡信号。

公开(公告)号：US4109110A

公开(公告)日：1978-08-22

申请号：US796919

申请日：1977-05-16

申请人： Michael John Gingell

发明人： Michael John Gingell

IPC分类号： G06F7/68 ,  H03M1/00 ,  H04J15/00 ,  H03K13/24

CPC分类号： G06F7/68 ,  H03M1/822 ,  H03M1/1014 ,  H03M1/84

摘要： The sample rate of the digital input is increased to a point where by reducing the number of bits per sample the final digital-to-analog conversion can be accomplished in a rate multiplier.