公开(公告)号：US12021077B2

公开(公告)日：2024-06-25

申请号：US18166860

申请日：2023-02-09

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad ,  Mikhail Yurievich Semenov ,  Yury Vladimirovich Alymov ,  Elena Valentinovna Somova

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0281 ,  H01L27/0255 ,  H01L27/0288 ,  H01L27/0296 ,  H02H9/045

Abstract: Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

公开(公告)号：US10014290B2

公开(公告)日：2018-07-03

申请号：US14989211

申请日：2016-01-06

Applicant: SK hynix Inc.

Inventor： Jong Su Kim

IPC: H02H9/00 ,  H01L27/02 ,  H02H9/04 ,  H01L27/06

CPC classification number: H01L27/0281 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/0629 ,  H02H9/046

Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

公开(公告)号：US20180061825A1

公开(公告)日：2018-03-01

申请号：US15647187

申请日：2017-07-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xueguang Hao ,  Yong Qiao ,  Hongfei Cheng ,  Xinyin Wu

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0281 ,  G02F1/136204 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/1244

Abstract: An electrostatic protection circuit, a display panel, and a display apparatus are disclosed. The electrostatic protection circuit comprises a switch control unit, a first electrostatic storage unit configured to store charges, and a second electrostatic storage unit configured to store charges, wherein the first electrostatic storage unit has a first terminal connected to a driving line and a second terminal connected to the switch control unit, and the second electrostatic storage unit has a first terminal connected to the switch control unit and a second terminal connected to a common electrode trace. With the first electrostatic storage unit connected to the driving line and the second electrostatic storage unit connected to the common electrode trace, the electrostatic protection circuit, the display panel, and the display apparatus according to the present disclosure can prevent leakage current on the driving line from flowing into the common electrode trace or prevent leakage current on the common electrode trace from flowing into the driving line after the switch control unit is switched off, which otherwise causes voltage fluctuation on the driving line or the common electrode trace thereby affecting the display quality.

公开(公告)号：US20170291415A1

公开(公告)日：2017-10-12

申请号：US15460408

申请日：2017-03-16

Applicant: CANON KABUSHIKI KAISHA

Inventor： Kohei Matsumoto ,  Kazunari Fujii

IPC: B41J2/14 ,  H01L27/02 ,  H02H9/04

CPC classification number: B41J2/14 ,  B41J2/04511 ,  B41J2/04541 ,  B41J2/0458 ,  B41J2/14072 ,  B41J2202/13 ,  H01L21/76202 ,  H01L27/0281 ,  H01L27/0285 ,  H01L27/0288 ,  H01L27/0292 ,  H01L29/7816 ,  H02H9/045

Abstract: A semiconductor device is provided. The device comprises: a first transistor that includes a first primary terminal, a second primary terminal and a first control terminal; a second transistor that includes a third primary terminal, a fourth primary terminal and a second control terminal; and a resistive element. The first and third primary terminal are connected to a first voltage line. The second primary terminal and one terminal of the resistive element are connected to a second voltage line. The first and second control terminal, the fourth primary terminal and the other terminal of the resistive element are connected to a node. A potential change in the third primary terminal is transmitted to the first control terminal by capacitive coupling between the third primary terminal and the node, turning on the first transistor.

公开(公告)号：US20180012886A1

公开(公告)日：2018-01-11

申请号：US15203296

申请日：2016-07-06

Applicant: Christopher P. Mozak ,  Victor Zia ,  Gabriel J. Thompson

Inventor： Christopher P. Mozak ,  Victor Zia ,  Gabriel J. Thompson

IPC: H01L27/02

CPC classification number: H01L27/0281 ,  H01L27/0255 ,  H02H9/046

Abstract: Some embodiments include apparatus and methods using a first transistor coupled between a node and a supply node, a second transistor coupled between the node and a ground node, an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node, and a transistor coupled between the additional node and the supply node.

公开(公告)号：US09219055B2

公开(公告)日：2015-12-22

申请号：US13517849

申请日：2012-06-14

Applicant: James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Nathan D. Jack ,  Jun Jun Li ,  Souvick Mitra

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Nathan D. Jack ,  Jun Jun Li ,  Souvick Mitra

IPC: H03K19/086 ,  H03K19/0175 ,  H01L27/02

CPC classification number: H02H9/005 ,  G06F17/5081 ,  H01L27/0251 ,  H01L27/0281 ,  H01L27/0285 ,  H02H9/04 ,  H02H9/046 ,  H03K17/687

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract translation: 具有CML驱动器的集成电路，其包括驱动器偏置网络。 第一输出焊盘和第二输出焊盘连接到电压焊盘。 第一驱动器连接到第一输出焊盘和电压焊盘。 第二驱动器连接到第二输出焊盘和电压焊盘。 第一ESD电路连接到电压焊盘，第一输出焊盘和第一驱动器。 第二ESD电路连接到电压焊盘，第二输出焊盘和第二驱动器。 当在第一输出焊盘处发生ESD事件时，第一ESD电路将第一驱动器偏压到电压焊盘的电压，并且当在第二ESD处发生ESD事件时，第二ESD电路将第二驱动器偏压到电压焊盘的电压 输出板。

公开(公告)号：US20150363539A1

公开(公告)日：2015-12-17

申请号：US14827526

申请日：2015-08-17

Applicant: International Business Machines Corporation

Inventor： James P. Di Sarro ,  Robert J. Gauthier ,  Nathan D. Jack ,  JunJun Li ,  Souvick Mitra

IPC: G06F17/50

CPC classification number: H02H9/005 ,  G06F17/5081 ,  H01L27/0251 ,  H01L27/0281 ,  H01L27/0285 ,  H02H9/04 ,  H02H9/046 ,  H03K17/687

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

公开(公告)号：US20140003621A1

公开(公告)日：2014-01-02

申请号：US14017037

申请日：2013-09-03

Applicant: CONEXANT SYSTEMS, INC.

Inventor： CHRISTIAN LARSEN ,  LORENZO CRESPI

IPC: H03G3/34 ,  H03K17/16

CPC classification number: H03K17/161 ,  H01L27/0281 ,  H03F1/305 ,  H03F3/181 ,  H03F2200/03 ,  H03F2200/249 ,  H03F2200/411 ,  H03F2200/414 ,  H03F2200/417 ,  H03G3/348 ,  H03K17/6871 ,  H03K2217/0018

Abstract: A grounding switch is described which operates properly even in the presence of negative voltages on a signal line. The grounding switch uses isolated field effect transistors that have their substrates tied to different voltages. The isolated field effect transistor has a gate voltage and substrate voltage which can be pulled down to a negative voltage when the signal line has a negative voltage allowing the switch to remain open even with a negative voltage.

Abstract translation: 描述了即使在信号线上存在负电压的情况下也能正常工作的接地开关。 接地开关使用隔离的场效应晶体管，将其衬底连接到不同的电压。 隔离的场效应晶体管具有栅极电压和衬底电压，当信号线具有负电压时，该电压可以被下拉至负电压，从而允许开关即使具有负电压也保持开路。

公开(公告)号：US08526635B2

公开(公告)日：2013-09-03

申请号：US12828716

申请日：2010-07-01

Applicant: Christian Larsen ,  Lorenzo Crespi

Inventor： Christian Larsen ,  Lorenzo Crespi

IPC: H04B15/00

CPC classification number: H03K17/161 ,  H01L27/0281 ,  H03F1/305 ,  H03F3/181 ,  H03F2200/03 ,  H03F2200/249 ,  H03F2200/411 ,  H03F2200/414 ,  H03F2200/417 ,  H03G3/348 ,  H03K17/6871 ,  H03K2217/0018

Abstract: A grounding switch is described which operates properly even in the presence of negative voltages on a signal line. The grounding switch uses isolated field effect transistors that have their substrates tied to different voltages. The isolated field effect transistor has a gate voltage and substrate voltage which can be pulled down to a negative voltage when the signal line has a negative voltage allowing the switch to remain open even with a negative voltage.

Abstract translation: 描述了即使在信号线上存在负电压的情况下也能正常工作的接地开关。 接地开关使用隔离的场效应晶体管，将其衬底连接到不同的电压。 隔离的场效应晶体管具有栅极电压和衬底电压，当信号线具有负电压时，该电压可以被下拉至负电压，从而允许开关即使具有负电压也保持开路。

公开(公告)号：US20110063763A1

公开(公告)日：2011-03-17

申请号：US12560475

申请日：2009-09-16

Applicant: David ALVAREZ ,  Krzysztof DOMANSKI ,  Gernot LANGGUTH ,  Christian RUSS ,  Wolfgang SOLDNER

Inventor： David ALVAREZ ,  Krzysztof DOMANSKI ,  Gernot LANGGUTH ,  Christian RUSS ,  Wolfgang SOLDNER

IPC: H02H9/04 ,  H01L27/088

CPC classification number: H01L27/0281 ,  H01L27/0285

Abstract: Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.

Abstract translation: 本文给出了包括静电放电（ESD）保护电路的实现。 ESD保护电路包括第一晶体管和第二晶体管。 第一晶体管具有耦合到第一电源线的第一端子和耦合到第二电源线的本体。 第二晶体管具有耦合到第二电源线的第一端子，耦合到第一电源线的体和耦合到第一晶体管的第二端子以限定受保护节点的第二端子。 ESD保护电路还包括具有耦合到受保护节点的第一端子的限流元件。