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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20110300690A1

    公开(公告)日：2011-12-08

    申请号：US13187754

    申请日：2011-07-21

    Applicant: Akihisa SHIMOMURA ,  Tatsuya MIZOI ,  Hidekazu MIYAIRI ,  Koichiro TANAKA

    Inventor： Akihisa SHIMOMURA ,  Tatsuya MIZOI ,  Hidekazu MIYAIRI ,  Koichiro TANAKA

    IPC: H01L21/30

    CPC classification number: H01L27/1266 ,  H01L21/02002 ,  H01L21/02038 ,  H01L21/3043 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772 ,  H01L51/5206 ,  H01L2251/554

    Abstract: To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first bonding substrate having first projections is attached to a base substrate. Then, the first bonding substrate is separated at the first projections so that first semiconductor films are formed over the base substrate. Next, a second bonding substrate having second projections is attached to the base substrate so that the second projections are placed in regions different from regions where the first semiconductor films are formed. Subsequently, the second bonding substrate is separated at the second projections so that second semiconductor films are formed over the base substrate. In the second bonding substrate, the width of each second projection in a direction (a depth direction) perpendicular to the second bonding substrate is larger than the film thickness of each first semiconductor film formed first.

    Abstract translation: 提供一种制造半导体器件的方法，其中在多个位置处转移的半导体膜之间的空间变窄。 具有第一突起的第一接合衬底附接到基底衬底。 然后，第一接合基板在第一突起处分离，使得第一半导体膜形成在基底基板上。 接下来，具有第二突起的第二接合基板被附接到基底基板，使得第二突起被放置在与形成第一半导体膜的区域不同的区域中。 随后，第二接合基板在第二突起处分离，使得第二半导体膜形成在基底基板上。 在第二接合基板中，与第二接合基板垂直的方向（深度方向）上的每个第二突起的宽度大于首先形成的第一半导体膜的膜厚。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20110207294A1

    公开(公告)日：2011-08-25

    申请号：US13027551

    申请日：2011-02-15

    Applicant: Masayuki NAKANISHI ,  Tetsuji Togawa ,  Kenya Ito ,  Masaya Seki ,  Kenji Iwade ,  Takeo Kubota

    Inventor： Masayuki NAKANISHI ,  Tetsuji Togawa ,  Kenya Ito ,  Masaya Seki ,  Kenji Iwade ,  Takeo Kubota

    IPC: H01L21/762

    CPC classification number: H01L21/02038 ,  B24B9/065 ,  B24B21/002 ,  B24B37/042 ,  H01L21/02087 ,  H01L21/304 ,  H01L21/76256

    Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes: pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon; and pressing a second polishing tape against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.

    Abstract translation: 一种制造半导体器件的方法使得可以在抛光条件下，在特别适用于沉积膜的抛光条件和沉积膜下面的硅的抛光条件下，用研磨带有效地抛光硅衬底的周边部分。 该方法包括：在第一旋转速度旋转器件基板的同时，将第一研磨带压在具有沉积膜的器件基板的周边部分上，同时以第一转速旋转器件基板，从而去除位于器件基板周边部分的沉积膜 并暴露下面的硅; 并且在第二旋转速度旋转所述装置基板的同时将第二研磨带压靠在所述装置基板的周边部分中的暴露的硅上，从而将所述硅抛光至预定的深度。

    Method of manufacturing semiconductor device
    4.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07989316B2

    公开(公告)日：2011-08-02

    申请号：US12824775

    申请日：2010-06-28

    Applicant: Akihisa Shimomura ,  Tatsuya Mizoi ,  Hidekazu Miyairi ,  Koichiro Tanaka

    Inventor： Akihisa Shimomura ,  Tatsuya Mizoi ,  Hidekazu Miyairi ,  Koichiro Tanaka

    IPC: H01L21/30

    CPC classification number: H01L27/1266 ,  H01L21/02002 ,  H01L21/02038 ,  H01L21/3043 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772 ,  H01L51/5206 ,  H01L2251/554

    Abstract: To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first bonding substrate having first projections is attached to a base substrate. Then, the first bonding substrate is separated at the first projections so that first semiconductor films are formed over the base substrate. Next, a second bonding substrate having second projections is attached to the base substrate so that the second projections are placed in regions different from regions where the first semiconductor films are formed. Subsequently, the second bonding substrate is separated at the second projections so that second semiconductor films are formed over the base substrate. In the second bonding substrate, the width of each second projection in a direction (a depth direction) perpendicular to the second bonding substrate is larger than the film thickness of each first semiconductor film formed first.

    Abstract translation: 提供一种制造半导体器件的方法，其中在多个位置处转移的半导体膜之间的空间变窄。 具有第一突起的第一接合衬底附接到基底衬底。 然后，第一接合基板在第一突起处分离，使得第一半导体膜形成在基底基板上。 接下来，具有第二突起的第二接合基板被附接到基底基板，使得第二突起被放置在与形成第一半导体膜的区域不同的区域中。 随后，第二接合基板在第二突起处分离，使得第二半导体膜形成在基底基板上。 在第二接合基板中，与第二接合基板垂直的方向（深度方向）上的每个第二突起的宽度大于首先形成的第一半导体膜的膜厚。

    PRINTHEAD AND RELATED METHODS AND SYSTEMS
    8.
    发明申请
    PRINTHEAD AND RELATED METHODS AND SYSTEMS 有权
    PRINTHEAD及相关方法和系统

    公开(公告)号：US20130106961A1

    公开(公告)日：2013-05-02

    申请号：US13695780

    申请日：2010-05-27

    Applicant: Andrew L. Van Brocklin ,  Eric L. Nikkel

    Inventor： Andrew L. Van Brocklin ,  Eric L. Nikkel

    IPC: B41J2/045 ,  H01L21/02

    CPC classification number: B41J2/04581 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1626 ,  B41J2002/14354 ,  B41J2002/14467 ,  B41J2202/13 ,  H01L21/02038

    Abstract: A printhead includes a moveable membrane, a piezoelectric actuator to move the membrane, and electronic circuitry disposed on the moveable membrane. A method of fabricating a printhead includes fabricating CMOS circuitry on a first side of a circuit wafer, and forming a chamber in a second side of the circuit wafer such that a bottom of the chamber forms a moveable membrane and the CMOS circuitry is disposed on the moveable membrane opposite the bottom of the chamber. A printing system includes a printhead having CMOS circuitry formed on a first side of a moveable membrane, a chamber having a bottom comprising a second side of the moveable membrane, and a piezoelectric actuator formed over the CMOS circuitry, configured to cause displacement of the moveable membrane into the chamber.

    Abstract translation: 打印头包括可移动膜，用于移动膜的压电致动器和设置在可移动膜上的电子电路。 制造打印头的方法包括在电路晶片的第一侧上制造CMOS电路，并且在电路晶片的第二侧形成一个室，使得该室的底部形成可移动膜，并且将该CMOS电路设置在该电路晶片上 可移动的膜与腔室的底部相对。 打印系统包括具有形成在可移动膜的第一侧上的CMOS电路的打印头，具有包括可移动膜的第二侧的底部的室以及形成在CMOS电路上的压电致动器，该压电致动器构造成使可移动膜的位移 膜进入腔室。

    Devices with gate-to-gate isolation structures and methods of manufacture
    9.
    发明授权
    Devices with gate-to-gate isolation structures and methods of manufacture 有权
    具有栅极到栅极隔离结构的器件和制造方法

    公开(公告)号：US09041107B2

    公开(公告)日：2015-05-26

    申请号：US13833735

    申请日：2013-03-15

    Applicant: International Business Machines Corporation

    Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    IPC: H01L27/12 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/84

    CPC classification number: H01L29/0649 ,  H01L21/02038 ,  H01L21/76283 ,  H01L21/845

    Abstract: Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.

    Abstract translation: 提供具有栅极到栅极隔离结构和制造方法的器件。 该方法包括在衬垫膜和下面的衬底中形成多个隔离结构。 该方法还包括形成包括隔离结构的多个翅片和包括两个垫片膜的第二多个翅片以及下面的衬底的一部分，每个鳍片由沟槽分开。 该方法还包括去除第二多个翅片的部分，导致比包括隔离结构的多个翅片的高度低的高度。 该方法还包括在每个沟槽内形成栅电极，将第二多个鳍片和包括隔离结构的多个翅片的邻接侧面相互掩埋。 包括隔离结构的多个翅片电和物理地隔离栅电极的相邻栅电极。

    Devices with gate-to-gate isolation structures and methods of manufacture
    10.
    发明授权
    Devices with gate-to-gate isolation structures and methods of manufacture 有权

    公开(公告)号：US09040383B2

    公开(公告)日：2015-05-26

    申请号：US13772993

    申请日：2013-02-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    IPC: H01L21/76 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/84

    CPC classification number: H01L29/0649 ,  H01L21/02038 ,  H01L21/76283 ,  H01L21/845

    Abstract: Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.

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