公开(公告)号：US20230386862A1

公开(公告)日：2023-11-30

申请号：US18447409

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L23/00 ,  B23K1/00 ,  H01L21/60

CPC分类号： H01L21/50 ,  H01L21/4853 ,  H01L24/10 ,  B23K1/0016 ,  H01L2021/60225 ,  H01L2021/60135

摘要： A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US11830746B2

公开(公告)日：2023-11-28

申请号：US17141835

申请日：2021-01-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC分类号： B23K1/00 ,  H01L21/50 ,  H01L21/48 ,  H01L23/00 ,  H01L21/60

CPC分类号： H01L21/50 ,  B23K1/0016 ,  H01L21/4853 ,  H01L24/10 ,  H01L2021/60135 ,  H01L2021/60225

摘要： A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US20170229426A1

公开(公告)日：2017-08-10

申请号：US15277349

申请日：2016-09-27

申请人： POWERTECH TECHNOLOGY INC.

发明人： Ching Wei HUNG ,  Wen-Jeng FAN

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L25/0657 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/04 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60225 ,  H01L2224/02166 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/3511

摘要： Disclosed is a fan-out back-to-back chip stacked package, comprising a back-to-back stack of a first chip and a second chip, an encapsulant, a plurality of vias disposed in the encapsulant, a first redistribution layer and a second redistribution layer. The encapsulant encapsulates the sides of the first chip and the sides of the second chip simultaneously and has a thickness not greater than the chip stacked height to expose a first active surface of the first chip and a second active surface of the second chip. The encapsulant has a first peripheral surface expanding from the first active surface and a second peripheral surface expanding from the second active surface. The first redistribution layer is formed on the first active surface and extended onto the first peripheral surface to electrically connect the first chip to the vias in the encapsulant. The second RDL is formed on the second active surface and extended onto the second peripheral surface to electrically connect the second chip to the vias in the encapsulant. Accordingly, the structure realizes a thin package configuration of multi-chip back-to-back stacking to reduce package warpage.

公开(公告)号：US20240347386A1

公开(公告)日：2024-10-17

申请号：US18299368

申请日：2023-04-12

申请人： Honeywell International Inc.

发明人： James L. Tucker ,  Eric E. Vogt ,  James W, Karcz, JR.

IPC分类号： H01L21/822 ,  H01L23/373 ,  H01L23/50

CPC分类号： H01L21/8221 ,  H01L23/3733 ,  H01L23/50 ,  H01L2021/60097 ,  H01L2021/60225

摘要： A semiconductor assembly including: a first semiconductor having a plurality of electrical contacts extending from an upper surface of the first semiconductor; a second semiconductor adjacent to the first semiconductor; and a mesh disposed between and affixed to the upper surface of the first semiconductor and the lower surface of the second semiconductor. A lower surface of the second semiconductor is electrically connected to the first semiconductor via the plurality of electrical contacts. The mesh comprises a plurality of interconnecting struts defining a plurality of openings, wherein the plurality of openings is configured to receive the plurality of electrical contacts.