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    METHODS AND STRUCTURE FOR TASK MANAGEMENT IN STORAGE CONTROLLERS OF A CLUSTERED STORAGE SYSTEM
    1.
    发明申请
    METHODS AND STRUCTURE FOR TASK MANAGEMENT IN STORAGE CONTROLLERS OF A CLUSTERED STORAGE SYSTEM 有权
    集群存储系统存储控制器中的任务管理方法与结构

    公开(公告)号：US20130067161A1

    公开(公告)日：2013-03-14

    申请号：US13432131

    申请日：2012-03-28

    申请人： Rakesh Chandra ,  James A. Rizzo ,  Vinu Velayudhan ,  Senthil M. Thangaraj ,  Sumant K. Patro

    发明人： Rakesh Chandra ,  James A. Rizzo ,  Vinu Velayudhan ,  Senthil M. Thangaraj ,  Sumant K. Patro

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0631 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0683 ,  G06F13/12 ,  G06F13/28 ,  G06F13/423 ,  G06F2206/1012 ,  Y02D10/14

    摘要： Methods and structure for task management in storage controllers of a clustered storage system. An initiator storage controller of the clustered storage system ships I/O requests for processing to a target storage controller of the system. Responsive to a need to abort a previously shipped I/O request, the initiator storage controller transmits a task management message to the target storage controller. The task management message identifies one or more previously shipped I/O requests to be aborted. The target storage controller processes the received task management message in due course of processing requests and completes processing for the aborted previously shipped request in an orderly manner. Resources associated with the aborted previously shipped requests are release within both controllers.

    摘要翻译： 集群存储系统存储控制器中任务管理的方法和结构。 集群存储系统的启动器存储控制器向系统的目标存储控制器发送用于处理的I / O请求。 响应于需要中止先前发布的I / O请求，发起者存储控制器向目标存储控制器发送任务管理消息。 任务管理消息标识一个或多个以前发送的I / O请求被中止。 目标存储控制器在处理请求的适当过程中处理所接收的任务管理消息，并且以有序的方式完成对中止的先前发送的请求的处理。 与先前发货的请求相关联的资源将在两个控制器内发布。

    METHODS AND STRUCTURE FOR IMPROVED PROCESSING OF I/O REQUESTS IN FAST PATH CIRCUITS OF A STORAGE CONTROLLER IN A CLUSTERED STORAGE SYSTEM
    2.
    发明申请
    METHODS AND STRUCTURE FOR IMPROVED PROCESSING OF I/O REQUESTS IN FAST PATH CIRCUITS OF A STORAGE CONTROLLER IN A CLUSTERED STORAGE SYSTEM 有权
    存储控制器在集群存储系统快速路径电路中对I / O请求进行改进的方法和结构

    公开(公告)号：US20130067125A1

    公开(公告)日：2013-03-14

    申请号：US13432213

    申请日：2012-03-28

    申请人： James A. Rizzo ,  Vinu Velayudhan ,  Adam Weiner ,  Gerald E. Smith

    发明人： James A. Rizzo ,  Vinu Velayudhan ,  Adam Weiner ,  Gerald E. Smith

    IPC分类号： G06F3/00

    CPC分类号： G06F3/0631 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0683 ,  G06F13/12 ,  G06F13/28 ,  G06F13/423 ,  G06F2206/1012 ,  Y02D10/14

    摘要： Methods and structure for improved processing of fast path I/O requests in a clustered storage system. In a storage controller of a clustered storage system, the controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing stack (typically implemented as programmed instructions) for processing I/O requests from a host system directed to a logical volume. Based on detecting a change of ownership of a device or volume and/or a change to logical to physical mapping of a logical volume, fast path I/O requests may be converted to logical volume requests based on mapping context information within the fast path I/O request and shipped within the clustered storage system for processing.

    摘要翻译： 用于改进集群存储系统中快速路径I / O请求处理的方法和结构。 在集群存储系统的存储控制器中，控制器包括与主机系统驱动程序紧密耦合的快速路径I / O请求处理电路，用于快速处理针对逻辑卷的存储设备的请求。 控制器还包括用于处理来自指向逻辑卷的主机系统的I / O请求的逻辑卷I / O处理堆栈（通常被实现为编程指令）。 基于检测设备或卷的所有权的变化和/或对逻辑卷的逻辑与物理映射的变化，可以基于快速路径I内的映射上下文信息将快速路径I / O请求转换为逻辑卷请求 / O请求并在集群存储系统内发货以进行处理。

    DATA RATE AND PVT ADAPTATION WITH PROGRAMMABLE BIAS CONTROL IN A SERDES RECEIVER
    3.
    发明申请
    DATA RATE AND PVT ADAPTATION WITH PROGRAMMABLE BIAS CONTROL IN A SERDES RECEIVER 有权
    数据速率和PVT适应与可编程偏移控制在服务器接收器

    公开(公告)号：US20160142233A1

    公开(公告)日：2016-05-19

    申请号：US14541345

    申请日：2014-11-14

    申请人： LSI Corporation

    发明人： Mohammad S. Mobin ,  Weiwei Mao ,  Brett D. Hardy

    IPC分类号： H04L27/01 ,  H04L7/00

    CPC分类号： H04L7/0079 ,  H03G3/3078 ,  H04L25/0298 ,  H04L25/03878

    摘要： Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition.

    摘要翻译： 描述的实施例在SerDes设备中提供了一种通过基于过程，电压，温度（PVT）和数据速率变化的可编程偏置来调整数据路径增益的自适应过程。 这种适应过程扩展了偏置电流动态范围，低频增益可编程为任何PVT和数据速率角下的给定可变增益放大器（VGA）设置的期望目标值范围。 接收（RX）数据路径结构通过基于感测的PVT和数据速率变化的可编程偏置来自适应数据路径增益。 低频衰减/增益范围扩展，并且可以通过在任何给定的PVT和数据速率条件下的给定VGA和线性均衡器（LEQ）设置的SerDes设备RX自适应处理来编程到期望的目标范围。

    FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION
    4.
    发明申请
    FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION 有权
    基于关联的LLR值的固定点转换

    公开(公告)号：US20150339189A1

    公开(公告)日：2015-11-26

    申请号：US14282380

    申请日：2014-05-20

    申请人： LSI Corporation

    发明人： Yunxiang Wu ,  Yu Cai ,  Erich F. Haratsch

    IPC分类号： G06F11/10

    CPC分类号： H03M13/3927 ,  G06F8/65 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/3905 ,  H03M13/6325 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6588 ,  H03M13/6591

    摘要： An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value.

    摘要翻译： 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读/写操作。 存储器包括多个存储器单元，每个存储器单元的尺寸小于存储器的总大小。 控制器可以被配置为对存储器单元执行纠错码解码。 控制器可以被配置为生成各自包含实际值的多个原始对数似然比。 控制器可以被配置为将每个原始对数似然比转换成包括固定点值的转换对数似然比。 转换包括（a）缩小每个原始对数似然比的大小，以及（b）将具有缩小幅度的原始对数似然比中的每一个舍入到固定点值。

    Temporal Tracking of Cache Data
    5.
    发明申请
    Temporal Tracking of Cache Data 有权
    缓存数据的时间跟踪

    公开(公告)号：US20150324295A1

    公开(公告)日：2015-11-12

    申请号：US14276429

    申请日：2014-05-13

    申请人： LSI Corporation

    发明人： Vinay Bangalore Shivashankaraiah ,  Kumaravel Thillai

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0871 ,  G06F12/0802 ,  G06F12/122 ,  G06F12/126 ,  G06F2212/26 ,  G06F2212/28 ,  G06F2212/604 ,  G06F2212/69

    摘要： A data storage system with a cache organizes cache windows into lists based on the number of cache lines accessed during input/output operations. The lists are maintained in temporal queues with cache windows transferred from prior temporal queues to a current temporal queue. Cache windows are removed from the oldest temporal queue and least accessed cache window list whenever cached data needs to be removed for new hot data.

    摘要翻译： 具有缓存的数据存储系统基于在输入/输出操作期间访问的高速缓存行的数量将高速缓存窗口组织到列表中。 列表被保持在具有从先前的时间队列传递到当前时间队列的高速缓存窗口的时间队列中。 每当需要为新的热数据移除缓存的数据时，缓存窗口将从最旧的时间队列和最少访问的缓存窗口列表中删除。

    MULTIPLEXED SYNCHRONOUS SERIAL PORT COMMUNICATION WITH SKEW CONTROL FOR STORAGE DEVICE
    6.
    发明申请
    MULTIPLEXED SYNCHRONOUS SERIAL PORT COMMUNICATION WITH SKEW CONTROL FOR STORAGE DEVICE 有权
    用于存储设备的多路同步串行通信

    公开(公告)号：US20150318030A1

    公开(公告)日：2015-11-05

    申请号：US14267344

    申请日：2014-05-01

    申请人： LSI Corporation

    发明人： Ross S. Wilson ,  David W. Kelly ,  Daniel J. Dolan ,  Richard Rauschmayer

    IPC分类号： G11C7/10

    CPC分类号： G06F3/06 ,  G06F13/4273 ,  G11C7/1072

    摘要： A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.

    摘要翻译： 例如，提供了一种在存储设备中实现控制器与前置放大器之间的多路复用通信的方法。 例如，通过控制数字总线的双向串行数据线来实现多路复用通信，以响应于方向选择性地将从控制器的第一方向到前置放大器的数字信号或从前置放大器到控制器的第二方向 控制信号，同时通过数字总线的时钟信号线从控制器向前置放大器发送同步时钟信号，以同步数字总线双向串行数据线上发送的数字信号的传送和处理。 方向控制信号在双向串行数据线和数字总线的时钟信号线之一上从控制器发送到前置放大器。

    DATA SCRAMBLING INITIALIZATION
    8.
    发明申请
    DATA SCRAMBLING INITIALIZATION 有权
    数据扫描初始化

    公开(公告)号：US20150312037A1

    公开(公告)日：2015-10-29

    申请号：US14267653

    申请日：2014-05-01

    申请人： LSI Corporation

    发明人： Harvey J Newman

    IPC分类号： H04L9/08 ,  G06F13/42

    CPC分类号： H04L9/0869 ,  G09C1/00 ,  H04L9/065 ,  H04L9/12 ,  H04L2209/34

    摘要： Systems and methods for improved synchronization between a transmit device and a receive device in a communication system. In one embodiment, an apparatus for transmitting bits of data over a link includes a scrambler to scramble data and circuitry configured to insert the scrambled data into frames and to transmit the frames in data blocks over the link. The apparatus also includes an initialization module configured to generate an unscrambled pseudo-random sequence. The circuitry is further configured to periodically insert the unscrambled pseudo-random sequence into a frame, to initialize the scrambler to a starting point based on the insertion of the unscrambled pseudo-random sequence into the frame, and to transmit the frame in a data block over the link.

    摘要翻译： 用于改善通信系统中发射设备和接收设备之间的同步的系统和方法。 在一个实施例中，用于通过链路发送数据位的装置包括扰频器，用于加扰数据和被配置为将加扰的数据插入到帧中并且通过链路在数据块中发送帧的电路。 该装置还包括被配置为生成未加扰的伪随机序列的初始化模块。 电路还被配置为将未加扰的伪随机序列周期性地插入到帧中，以便基于将未加扰的伪随机序列插入到帧中来将扰频器初始化为起始点，并且将数据块中的帧发送到数据块 在链接上。

    ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING
    10.
    发明申请
    ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING 审中-公开
    在线学习和软件信息学习

    公开(公告)号：US20150294739A1

    公开(公告)日：2015-10-15

    申请号：US14249714

    申请日：2014-04-10

    申请人： LSI Corporation

    发明人： Yu Cai ,  Zhengang Chen ,  Yunxiang Wu ,  Erich F. Haratsch

    IPC分类号： G11C29/50 ,  G06F11/10 ,  G06F11/07 ,  G11C29/44

    CPC分类号： G11C16/349 ,  G06F11/1012 ,  G11C11/5642 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/0411

    摘要： A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells.

    摘要翻译： 系统包括被配置为从多个存储单元读取信息的处理器。 处理器使用第一参考电压启动来自一组存储器单元的原始数据的第一次读取。 处理器还使用不同于第一参考电压的第二参考电压来启动来自存储器单元组的原始数据的第二次读取。 处理器进一步将第一次读取与第二次读取进行比较，以识别用第一次读取和第二次读取之间改变的位值读取的存储器单元。 处理器还将读取的存储器单元分配为在第一和第二读取之间变化到与第二参考电压相关联的区域的位值。 处理器进一步用改变的位值对读取的单元的数量进行计数，以产生对应于该组存储器单元的软信息的直方图。