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    PHASE CHANGE MEMORY
    1.
    发明申请
    PHASE CHANGE MEMORY 有权
    相变记忆

    公开(公告)号：US20110193047A1

    公开(公告)日：2011-08-11

    申请号：US13092725

    申请日：2011-04-22

    申请人： Yoon-Jong SONG ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    发明人： Yoon-Jong SONG ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

    摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

    摘要翻译： 制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度 大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面 硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

    VARIABLE RESISTANCE MEMORY
    2.
    发明申请
    VARIABLE RESISTANCE MEMORY 审中-公开
    可变电阻记忆

    公开(公告)号：US20120175580A1

    公开(公告)日：2012-07-12

    申请号：US13430042

    申请日：2012-03-26

    申请人： Yoon-Jong SONG ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    发明人： Yoon-Jong SONG ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

    摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

    摘要翻译： 制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度 大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面 硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20070272950A1

    公开(公告)日：2007-11-29

    申请号：US11753291

    申请日：2007-05-24

    申请人： Rak-Hwan KIM ,  Kyung-Chang RYOO ,  In-Sun PARK ,  Yoon-Jong SONG ,  Hyeon-Deok LEE ,  Hyun-Seok LIM

    发明人： Rak-Hwan KIM ,  Kyung-Chang RYOO ,  In-Sun PARK ,  Yoon-Jong SONG ,  Hyeon-Deok LEE ,  Hyun-Seok LIM

    IPC分类号： H01L27/10

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1666

    摘要： A method of fabricating a semiconductor memory device includes forming a first insulating layer and a sacrificial layer on a substrate. The first insulating layer and the sacrificial layer have an opening therein. A first conductive layer is formed in the opening and on the sacrificial layer. A second insulating layer is formed on the first conductive layer. The second insulating layer, the first conductive layer and the sacrificial layer are then planarized until the first insulating layer is exposed, thereby forming a first conductive pattern and a second insulating layer pattern in the opening. A phase change material layer is formed on the first conductive pattern, the first insulating layer and the second insulating layer pattern. A second conductive pattern is formed on the phase change material layer. A semiconductor memory device and a data processing system adopting the semiconductor memory device are also provided.

    摘要翻译： 制造半导体存储器件的方法包括在衬底上形成第一绝缘层和牺牲层。 第一绝缘层和牺牲层在其中具有开口。 在开口和牺牲层上形成第一导电层。 在第一导电层上形成第二绝缘层。 然后将第二绝缘层，第一导电层和牺牲层平坦化直到第一绝缘层露出，从而在开口中形成第一导电图案和第二绝缘层图案。 在第一导电图案，第一绝缘层和第二绝缘层图案上形成相变材料层。 在相变材料层上形成第二导电图案。 还提供了半导体存储器件和采用半导体存储器件的数据处理系统。

    PHASE-CHANGE MEMORY DEVICE
    4.
    发明申请
    PHASE-CHANGE MEMORY DEVICE 有权
    相变存储器件

    公开(公告)号：US20070284622A1

    公开(公告)日：2007-12-13

    申请号：US11754437

    申请日：2007-05-29

    申请人： Kyung-Chang Ryoo ,  Ju-Chul Park ,  Se-Ahn Song ,  Yoon-Jong SONG

    发明人： Kyung-Chang Ryoo ,  Ju-Chul Park ,  Se-Ahn Song ,  Yoon-Jong SONG

    IPC分类号： H01L29/76 ,  H01L29/745

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/144

    摘要： Disclosed is a phase-change memory device including a phase-change material pattern, a diffusion barrier layer, a bottom electrode and a top electrode. The phase-change material pattern is placed on the bottom electrode, and the diffusion barrier layer containing tellurium is placed on the phase-change material pattern. The top electrode containing titanium is placed on the diffusion barrier layer. The diffusion barrier layer acts to inhibit diffusion of titanium from the top electrode into the phase-change material pattern.

    摘要翻译： 公开了一种包括相变材料图案，扩散阻挡层，底部电极和顶部电极的相变存储器件。 将相变材料图案放置在底部电极上，并且将包含碲的扩散阻挡层放置在相变材料图案上。 将包含钛的顶部电极放置在扩散阻挡层上。 扩散阻挡层用于抑制钛从顶部电极扩散到相变材料图案中。

    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME
    5.
    发明申请
    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
    具有双下电极的相变存储器件及其制造方法

    公开(公告)号：US20080099753A1

    公开(公告)日：2008-05-01

    申请号：US11932781

    申请日：2007-10-31

    申请人： Yoon-Jong SONG ,  Kyung-Chang RYOO ,  Dong-Won LIM

    发明人： Yoon-Jong SONG ,  Kyung-Chang RYOO ,  Dong-Won LIM

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1675

    摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    SEMICONDUCTOR DEVICE INCLUDING UNIFORM CONTACT PLUGS AND A METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING UNIFORM CONTACT PLUGS AND A METHOD OF MANUFACTURING THE SAME 有权
    包含均匀接触片的半导体器件及其制造方法

    公开(公告)号：US20100200833A1

    公开(公告)日：2010-08-12

    申请号：US12697620

    申请日：2010-02-01

    申请人： Kyu-Rie SIM ,  Jung-Hoon PARK ,  Yoon-Jong SONG ,  Jae-Min SHIN ,  Shin-Hee HAN

    发明人： Kyu-Rie SIM ,  Jung-Hoon PARK ,  Yoon-Jong SONG ,  Jae-Min SHIN ,  Shin-Hee HAN

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24 ,  H01L27/222

    摘要： A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.

    摘要翻译： 提供半导体器件，半导体模块，电子设备及其制造和制造方法。 半导体器件包括形成在衬底上的下互连，形成在下互连上的多个控制图案，形成在控制图案上的多个下接触插塞图案，形成在下接触插塞图案上的多个存储图案， 形成在存储图案上的多个上电极和形成在上电极上的多个上互连。 下接触插头图案各自包括具有不同尺寸的至少两个接触孔，多个侧壁图案形成在两个接触孔的内侧壁上，并且其中侧壁图案具有彼此不同的厚度。 半导体器件还包括多个沿着侧壁图案的内侧形成并且具有小于10％的尺寸误差的电极图案，以及形成在电极图案内并且完全填充接触孔内部的多个填充图案。

    MAGNETIC MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    9.
    发明申请
    MAGNETIC MEMORY DEVICE AND METHOD FOR FORMING THE SAME 有权
    磁记忆体装置及其形成方法

    公开(公告)号：US20160020384A1

    公开(公告)日：2016-01-21

    申请号：US14656659

    申请日：2015-03-12

    申请人： Dae-Eun JEONG ,  Sang-Yong KIM ,  Yoon-Jong SONG

    发明人： Dae-Eun JEONG ,  Sang-Yong KIM ,  Yoon-Jong SONG

    IPC分类号： H01L43/08 ,  G11C11/16 ,  H01L43/02

    CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675 ,  G11C2013/0083 ,  H01L43/02 ,  H01L43/12

    摘要： Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.

    摘要翻译： 提供一种磁存储器件及其形成方法。 磁存储器件包括位于衬底上的磁性隧道结图案，其包括磁性图案和位于磁性图案之间的隧道势垒图案，以及位于磁性隧道结图案上的第一结晶保存图案，并且具有比 磁性图案。 第一个结晶保存图案是无定形的。

    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    磁性随机访问存储器件及其制造方法

    公开(公告)号：US20170069684A1

    公开(公告)日：2017-03-09

    申请号：US15157403

    申请日：2016-05-17

    申请人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

    发明人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

    IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    CPC分类号： H01L27/222 ,  H01L43/12

    摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

    摘要翻译： 制造MRAM器件的方法包括在衬底上依次形成第一绝缘层和蚀刻停止层。 通过蚀刻停止层和第一绝缘中间层形成下电极。 在下电极和蚀刻停止层上依次形成MTJ结构层和上电极。 通过使用上电极作为蚀刻掩模的物理蚀刻工艺对MTJ结构层进行构图，以形成至少部分地接触下电极的MTJ结构。 第一绝缘中间层由蚀刻停止层保护，因此不被物理蚀刻工艺蚀刻。