公开(公告)号：US20140112053A1

公开(公告)日：2014-04-24

申请号：US13659882

申请日：2012-10-24

申请人： YongSik Youn ,  SOOHO CHA ,  DongSeok Kang ,  Chan-kyung Kim

发明人： YongSik Youn ,  SOOHO CHA ,  DongSeok Kang ,  Chan-kyung Kim

IPC分类号： G11C7/06

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1084 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： Example embodiments include a level shifting write driver in a sense amplifier for a resistive type memory. The write driver may include a cross-coupled latch circuit, a first output section, a second output section, and an input section. The first output section includes one or more first driving transistors to drive a first current through the first output section and not through the cross-coupled latch. The second output section includes one or more second driving transistors configured to drive a second current through the second output section and not through the cross-coupled latch. The current flows of the outputs sections are isolated from the latch circuit. In some embodiments, no two PMOS type transistors are serially connected, thereby reducing the consumption of die area. In some embodiments, a single control signal is used to operate the write driver.

公开(公告)号：US08885386B2

公开(公告)日：2014-11-11

申请号：US13659882

申请日：2012-10-24

申请人： YongSik Youn ,  Sooho Cha ,  DongSeok Kang ,  Chan-kyung Kim

发明人： YongSik Youn ,  Sooho Cha ,  DongSeok Kang ,  Chan-kyung Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1084 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： Example embodiments include a level shifting write driver in a sense amplifier for a resistive type memory. The write driver may include a cross-coupled latch circuit, a first output section, a second output section, and an input section. The first output section includes one or more first driving transistors to drive a first current through the first output section and not through the cross-coupled latch. The second output section includes one or more second driving transistors configured to drive a second current through the second output section and not through the cross-coupled latch. The current flows of the outputs sections are isolated from the latch circuit. In some embodiments, no two PMOS type transistors are serially connected, thereby reducing the consumption of die area. In some embodiments, a single control signal is used to operate the write driver.

摘要翻译： 示例性实施例包括用于电阻型存储器的读出放大器中的电平移位写入驱动器。 写驱动器可以包括交叉耦合锁存电路，第一输出部分，第二输出部分和输入部分。 第一输出部分包括一个或多个第一驱动晶体管，以驱动通过第一输出部分的第一电流，而不是通过交叉耦合的锁存器。 第二输出部分包括一个或多个第二驱动晶体管，其构造成驱动第二电流通过第二输出部分而不通过交叉耦合的锁存器。 输出部分的电流流动与锁存电路隔离。 在一些实施例中，没有两个PMOS型晶体管串联连接，从而减少了管芯面积的消耗。 在一些实施例中，使用单个控制信号来操作写入驱动器。

公开(公告)号：US09070424B2

公开(公告)日：2015-06-30

申请号：US13538869

申请日：2012-06-29

申请人： YongSik Youn ,  Sooho Cha ,  Chan-kyung Kim

发明人： YongSik Youn ,  Sooho Cha ,  Chan-kyung Kim

IPC分类号： G11C11/00 ,  G11C7/06 ,  G11C13/00 ,  G11C11/16

CPC分类号： G11C7/065 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0042

摘要： Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

摘要翻译： 示例性实施例包括电阻型存储读出放大器电路，其包括差分输出端，第一和第二输入端，预充电部分和其他组件，其被布置为使得电流在至少“设置”或“放大”阶段期间重新使用 ，从而降低电路的总体电流消耗，并提高抗噪声能力。 响应于参考线电流和位线电流之间的增量平均电流，使高阻抗输出端子的电压电平摆动。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。 还公开了电流镜电路，其可以与所公开的读出放大器电路结合使用。 在另一个实施例中，读出放大器电路包括读/写 - 写操作的能力。

公开(公告)号：US08750018B2

公开(公告)日：2014-06-10

申请号：US13488432

申请日：2012-06-04

申请人： YongSik Youn ,  Adrian Ong ,  Sooho Cha ,  Chan-kyung Kim

发明人： YongSik Youn ,  Adrian Ong ,  Sooho Cha ,  Chan-kyung Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C7/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2207/063

摘要： Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

摘要翻译： 示例实施例包括包括差分输出端子，直接耦合到预充电晶体管的第一和第二输入端子，预充电晶体管和电流调制晶体管的电阻型存储电流读出放大器电路。 预充电配置提供高峰值电流，以在电流检测放大器电路的“准备”或“预充电”阶段期间为位线和参考线充电。 电流调制晶体管被配置为在至少“设置”或“放大”阶段期间以饱和区域模式工作。 电流调制晶体管在“设置”或“放大”级期间连续平均位线电流和参考线电流，从而提高电路的抗噪声能力。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。

公开(公告)号：US20140003124A1

公开(公告)日：2014-01-02

申请号：US13538869

申请日：2012-06-29

申请人： YongSik Youn ,  Sooho CHA ,  Chan-kyung Kim

发明人： YongSik Youn ,  Sooho CHA ,  Chan-kyung Kim

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0042

摘要： Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

摘要翻译： 示例性实施例包括电阻型存储读出放大器电路，其包括差分输出端，第一和第二输入端，预充电部分和其它组件，其被布置为使得电流在至少“设置”或“放大”阶段期间重新使用 ，从而降低电路的总体电流消耗，并提高抗噪声能力。 响应于参考线电流和位线电流之间的增量平均电流，使高阻抗输出端子的电压电平摆动。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。 还公开了电流镜电路，其可以与所公开的读出放大器电路结合使用。 在另一个实施例中，读出放大器电路包括读/写 - 写操作的能力。

公开(公告)号：US20130322154A1

公开(公告)日：2013-12-05

申请号：US13488432

申请日：2012-06-04

申请人： YongSik Youn ,  Adrian E. Ong ,  SOOHO CHA ,  Chan-kyung Kim

发明人： YongSik Youn ,  Adrian E. Ong ,  SOOHO CHA ,  Chan-kyung Kim

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/00

CPC分类号： G11C7/062 ,  G11C7/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2207/063

摘要： Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

摘要翻译： 示例实施例包括包括差分输出端子，直接耦合到预充电晶体管的第一和第二输入端子，预充电晶体管和电流调制晶体管的电阻型存储电流读出放大器电路。 预充电配置提供高峰值电流，以在电流检测放大器电路的“准备”或“预充电”阶段期间为位线和参考线充电。 电流调制晶体管被配置为在至少“设置”或“放大”阶段期间以饱和区域模式工作。 电流调制晶体管在“设置”或“放大”级期间连续平均位线电流和参考线电流，从而提高电路的抗噪声能力。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。

公开(公告)号：US08089320B2

公开(公告)日：2012-01-03

申请号：US12684332

申请日：2010-01-08

申请人： Chan-kyung Kim

发明人： Chan-kyung Kim

IPC分类号： H03B27/00

CPC分类号： H03L7/099 ,  H03K3/0231 ,  H03L2207/06

摘要： In one embodiment, the differential amplifier (DA) includes a first inverter inverting a first input signal and outputting the inverted first input signal to a current supply controller and a current drain controller. A second inverter inverts the first input signal and outputs the inverted first input signal as an output signal of the DA. The current supply controller supplies current to the first and second inverters in response to the inverted first input signal output from the first inverter during a first period. The current drain controller drains current from the first and second inverters in response to the inverted first input signal output from the first inverter during a second period. The output signal of the DA and the first input signal have differential phases with respect to each other and oscillate between logic high and low levels during the first period and the second period.

摘要翻译： 在一个实施例中，差分放大器（DA）包括反相第一输入信号并将反相的第一输入信号输出到电流供应控制器和电流消耗控制器的第一反相器。 第二个反相器将第一输入信号反相并输出反相的第一输入信号作为DA的输出信号。 电流供应控制器响应于在第一时段期间从第一逆变器输出的反相的第一输入信号，向第一和第二逆变器提供电流。 电流漏极控制器响应于在第二周期期间从第一反相器输出的反相的第一输入信号，从第一和第二反相器引出电流。 DA和第一输入信号的输出信号在第一周期和第二周期期间彼此具有差分相位并且在逻辑高电平和低电平之间振荡。

公开(公告)号：US07944244B2

公开(公告)日：2011-05-17

申请号：US12894631

申请日：2010-09-30

申请人： Sang-soon Lim ,  Chan-kyung Kim

发明人： Sang-soon Lim ,  Chan-kyung Kim

IPC分类号： H03K19/20

CPC分类号： H03K19/1736

摘要： Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal. The multi-function logic gate includes a pull-down switching unit having input switches of a second group being respectively connected to multiple input terminals and selection switches of the second group connected to either the selection terminal or the inverted selection terminal, the pull-down switching unit electrically connecting the input switches of the second group in parallel or in series between the output terminal and a ground terminal according to the logic levels of the selection terminal and the inverted selection terminal. The connection of the input switches of the second group is complementarily opposite to the connection of the input switches of the first group.

摘要翻译： 提供了能够通过使用单个逻辑门电路来执行多个逻辑运算的逻辑门装置。 多功能逻辑门装置包括上拉开关单元，其具有分别连接到多个输入端的第一组的输入开关和连接到选择端或逻辑反相选择端的第一组的选择开关，所述拉 所述开关单元根据所述选择端子和所述反相选择端子的逻辑电平将所述第一组的输入开关串联或并联连接在电源和输出端子之间。 多功能逻辑门包括下拉开关单元，其具有分别连接到多个输入端子的第二组的输入开关和连接到选择端子或反相选择端子的第二组的选择开关，下拉开关单元 开关单元根据选择端子和反相选择端子的逻辑电平将第二组的输入开关并联或串联连接在输出端子与接地端子之间。 第二组的输入开关的连接与第一组的输入开关的连接互补地相反。

公开(公告)号：US07830179B2

公开(公告)日：2010-11-09

申请号：US12276819

申请日：2008-11-24

申请人： Sang-soon Lim ,  Chan-kyung Kim

发明人： Sang-soon Lim ,  Chan-kyung Kim

IPC分类号： H03K19/20

CPC分类号： H03K19/1736

摘要： Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal. The multi-function logic gate includes a pull-down switching unit having input switches of a second group being respectively connected to multiple input terminals and selection switches of the second group connected to either the selection terminal or the inverted selection terminal, the pull-down switching unit electrically connecting the input switches of the second group in parallel or in series between the output terminal and a ground terminal according to the logic levels of the selection terminal and the inverted selection terminal. The connection of the input switches of the second group is complementarily opposite to the connection of the input switches of the first group.

摘要翻译： 提供了能够通过使用单个逻辑门电路来执行多个逻辑运算的逻辑门装置。 多功能逻辑门装置包括上拉开关单元，其具有分别连接到多个输入端的第一组的输入开关和连接到选择端或逻辑反相选择端的第一组的选择开关，所述拉 所述开关单元根据所述选择端子和所述反相选择端子的逻辑电平将所述第一组的输入开关串联或并联连接在电源和输出端子之间。 多功能逻辑门包括下拉开关单元，其具有分别连接到多个输入端子的第二组的输入开关和连接到选择端子或反相选择端子的第二组的选择开关，下拉开关单元 开关单元根据选择端子和反相选择端子的逻辑电平将第二组的输入开关并联或串联连接在输出端子与接地端子之间。 第二组的输入开关的连接与第一组的输入开关的连接互补地相反。

公开(公告)号：US07671651B2

公开(公告)日：2010-03-02

申请号：US11512155

申请日：2006-08-30

申请人： Chan-kyung Kim

发明人： Chan-kyung Kim

IPC分类号： H03L7/00

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K5/1565

摘要： A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

摘要翻译： 包括占空比校正电路的占空比校正电路和延迟锁定环（DLL）能够控制其工作，以正确地分析在DLL中产生占空比误差时产生占空比误差的原因 。 占空比校正电路选择性地输出到用于在切换控制信号的控制下控制与外部时钟信号同步的内部时钟信号的占空比的DLL核心占空比偏移信息。 DLL根据占空比偏移信息校正参考时钟信号的占空比，从而输出占空比为50％的参考时钟信号。