公开(公告)号：US5846865A

公开(公告)日：1998-12-08

申请号：US745468

申请日：1996-11-12

申请人： Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

发明人： Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC分类号： H01L27/11253 ,  H01L27/112 ,  Y10S148/02

摘要： A method of fabricating flat-cell mask ROM devices having buried bit-lines that will not be subject to punch-through between neighboring bit lines as a result of heating in subsequent steps after the buried bit-lines are formed. In the method, the first step is to prepare a semiconductor substrate with a gate oxide layer formed thereon. Thereafter, a first polysilicon layer is formed over the gate oxide layer, and a plurality of trenches at predetermined positions, with these trenches extending through the gate oxide and first polysilicon layer and into the substrate to a predetermined depth. Then, trenches are filled with tungsten to form a plurality of source/drain regions. A second polysilicon layer is then formed over the first polysilicon layer, and an insulating layers is formed over each of the source/drain regions. Thereafter, a third polysilicon layer is formed over the second polysilicon layer and the insulating layers, and finally the third polysilicon layer is defined to form a gate for the integrated circuit device. Since the source/drain regions are made of tungsten metal, the spacing distance therebetween will not be changed when subjected to high-temperature conditions during subsequent process steps. The punch-through effect can thus be avoided.

摘要翻译： 一种制造平面单元掩膜ROM器件的方法，其具有在形成掩埋位线之后的随后步骤中加热的结果之后不会在相邻位线之间穿透的掩埋位线。 在该方法中，第一步是制备其上形成有栅氧化层的半导体衬底。 此后，在栅极氧化物层上形成第一多晶硅层，并在预定位置形成多个沟槽，其中这些沟槽延伸穿过栅极氧化物和第一多晶硅层并进入衬底至预定深度。 然后，用钨填充沟槽以形成多个源极/漏极区域。 然后在第一多晶硅层上形成第二多晶硅层，并且在每个源/漏区上形成绝缘层。 此后，在第二多晶硅层和绝缘层上形成第三多晶硅层，最后形成第三多晶硅层以形成用于集成电路器件的栅极。 由于源极/漏极区域由钨金属制成，因此在后续工艺步骤中经受高温条件时，它们之间的间隔距离将不会改变。 因此可以避免穿透效果。

公开(公告)号：US5904540A

公开(公告)日：1999-05-18

申请号：US994987

申请日：1997-12-19

申请人： Yi-Chung Sheng ,  Jih-Wen Chou

发明人： Yi-Chung Sheng ,  Jih-Wen Chou

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A method for forming shallow trench isolation comprising the steps of providing a substrate having a mask layer formed thereon. Next, the mask layer is patterned to form a first trench in the substrate. Then, dielectric spacers are formed on the sidewalls of the first trench. After that, a second trench is formed in the substrate by an etching operation following the profile of the dielectric spacers. Next, a second dielectric layer is formed filling the second trench, wherein the second dielectric layer and the dielectric spacers are formed from different materials. Thereafter, the dielectric spacers are removed to form recess cavities, and then a filler material is deposited into the recess cavities. Subsequently, a gate oxide layer is formed over the filler material and the substrate. Finally, a polysilicon gate layer is formed over the gate oxide layer.

摘要翻译： 一种用于形成浅沟槽隔离的方法，包括以下步骤：提供其上形成有掩模层的衬底。 接下来，对掩模层进行图案化以在衬底中形成第一沟槽。 然后，在第一沟槽的侧壁上形成电介质间隔物。 之后，通过蚀刻操作在介质间隔物的轮廓之后，在衬底中形成第二沟槽。 接下来，形成填充第二沟槽的第二电介质层，其中第二电介质层和电介质间隔物由不同的材料形成。 此后，去除电介质间隔物以形成凹陷腔，然后将填充材料沉积到凹腔中。 接着，在填充材料和基板上形成栅氧化层。 最后，在栅极氧化物层上形成多晶硅栅极层。

公开(公告)号：US5891779A

公开(公告)日：1999-04-06

申请号：US9300

申请日：1998-01-20

申请人： Cheng-Hui Chung ,  Yi-Chung Sheng

发明人： Cheng-Hui Chung ,  Yi-Chung Sheng

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC分类号： H01L27/1128 ,  H01L27/112

摘要： A method of fabricating a tetra-state mask read only memory. A memory device is fabricated. Using a first photo-resist to dope the channel regions, a first coding step is performed to obtain a transistor having two different threshold voltage. Covering a gate oxide layer, and etching the first photo-resist layer to form a via, a buried bit line is formed. A poly-silicon layer is formed on the gate oxide layer. Doping the second poly-silicon layer by implanting ions to the source/drain regions, and using a second photo-resist layer, a second coding step is performed. An inverse transistor with two different threshold voltage is formed.

摘要翻译： 制造四态掩模只读存储器的方法。 制造存储器件。 使用第一光致抗蚀剂来掺杂沟道区，执行第一编码步骤以获得具有两个不同阈值电压的晶体管。 覆盖栅极氧化物层，蚀刻第一光致抗蚀剂层以形成通孔，形成掩埋位线。 在栅氧化层上形成多晶硅层。 通过将离子注入到源极/漏极区域来掺杂第二多晶硅层，并且使用第二光致抗蚀剂层，执行第二编码步骤。 形成具有两个不同阈值电压的反相晶体管。

公开(公告)号：US5854109A

公开(公告)日：1998-12-29

申请号：US863626

申请日：1997-05-27

申请人： Yi-Chung Sheng ,  Cheng-Hui Chung

发明人： Yi-Chung Sheng ,  Cheng-Hui Chung

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8234

CPC分类号： H01L27/11253 ,  H01L27/112

摘要： A self-aligned silicide process for the formation of a mask ROM includes forming a self-aligned silicide layer over the bit lines and the word lines to lower the resistance of the bit lines and word lines in the mask ROM.

摘要翻译： 用于形成掩模ROM的自对准硅化物工艺包括在位线和字线之上形成自对准的硅化物层，以降低掩模ROM中的位线和字线的电阻。

公开(公告)号：US5585296A

公开(公告)日：1996-12-17

申请号：US599923

申请日：1996-02-12

申请人： Cheng-Hui Chung ,  Yi-Chung Sheng ,  Belle Chia

发明人： Cheng-Hui Chung ,  Yi-Chung Sheng ,  Belle Chia

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/265

CPC分类号： H01L27/11253 ,  H01L27/112 ,  Y10S438/981

摘要： A method of fabricating memory cells with buried bit lines. In this method, a pad oxide layer is formed on a first conductivity-type silicon substrate. A photoresist layer is formed on the pad oxide layer while exposing predetermined areas of channels. A thick oxide layer is deposited by liquid phase deposition (LPD). The photoresist layer is removed. Second conductivity-type impurities are implanted to form source-drain electrodes using the thick oxide layer as a mask. The thick oxide layer and the pad oxide layer are removed to form bit lines and then word lines are formed crossing the bit lines, whereby the structure with buried bit lines and an array of memory cells is completed.

摘要翻译： 一种制造具有掩埋位线的存储单元的方法。 在该方法中，在第一导电型硅衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成光致抗蚀剂层，同时暴露预定区域的通道。 通过液相沉积（LPD）沉积厚的氧化物层。 去除光致抗蚀剂层。 注入第二导电型杂质以使用厚氧化物层作为掩模形成源 - 漏电极。 去除厚氧化物层和焊盘氧化物层以形成位线，然后形成与位线交叉的字线，由此完成具有掩埋位线和存储器单元阵列的结构。

公开(公告)号：US5668031A

公开(公告)日：1997-09-16

申请号：US658673

申请日：1996-06-04

申请人： Chen-Chiu Hsue ,  Cheng-Hui Chung ,  Yi-Chung Sheng

发明人： Chen-Chiu Hsue ,  Cheng-Hui Chung ,  Yi-Chung Sheng

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/70

CPC分类号： H01L27/11253 ,  H01L27/112

摘要： A method of fabricating a high density flat mask read only memory. At first a plurality of trenches are formed in a surface of a silicon substrate at predetermined desired source-drain electrodes areas. A dielectric layer is formed on at least the surface of the trenches. A first polysilicon layer is formed over the dielectric layer and then portions of the first polysilicon layer are removed to leave a portion thereof on the bottom of each trench. Using the first polysilicon layer as an etch stop layer, the dielectric layer is etched. A second polysilicon layer then is formed on the surface of the silicon substrate, the first polysilicon layer and the dielectric layer, and then the the second polysilicon layer is etched back to the substrate surface to form the source-drain electrode areas, that is, the bit lines. On the surface of the bit lines and the silicon substrate, a gate oxide layer and a third polysilicon layer are formed sequentially. Finally, the gate oxide layer and the third polysilicon layer are defined to form gate electrodes, that is, word lines for the memory.

摘要翻译： 一种制造高密度平面掩模只读存储器的方法。 首先，在预定的期望的源极 - 漏极电极区域的硅衬底的表面中形成多个沟槽。 在沟槽的至少表面上形成介电层。 在电介质层上形成第一多晶硅层，然后去除第一多晶硅层的部分，以将其部分留在每个沟槽的底部。 使用第一多晶硅层作为蚀刻停止层，蚀刻介电层。 然后在硅衬底，第一多晶硅层和电介质层的表面上形成第二多晶硅层，然后将第二多晶硅层回蚀刻到衬底表面以形成源极 - 漏极电极区域，即， 位线。 在位线和硅衬底的表面上依次形成栅氧化层和第三多晶硅层。 最后，栅极氧化物层和第三多晶硅层被定义为形成栅电极，即用于存储器的字线。

公开(公告)号：US08624398B2

公开(公告)日：2014-01-07

申请号：US12547521

申请日：2009-08-26

申请人： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

发明人： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

IPC分类号： H01L23/52

CPC分类号： G06F17/5081 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.

摘要翻译： 半导体电路结构包括基板和互连结构。 互连结构设置在衬底上并且包括多个电路图案和至少一个闭环图案。 闭环图案与电路图案处于相同的层中，在电路图案之间包围并与电路图案绝缘。 闭环图案可以保护电路图案不被应力损坏，以改善半导体电路结构的机械强度。

公开(公告)号：US06544849B2

公开(公告)日：2003-04-08

申请号：US09852254

申请日：2001-05-09

申请人： Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chang-Chi Huang ,  Sheng-Hao Lin ,  Cheng-Tung Huang

发明人： Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chang-Chi Huang ,  Sheng-Hao Lin ,  Cheng-Tung Huang

IPC分类号： H01L218234

CPC分类号： H01L21/823425

摘要： A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device. Since the offset spacers are formed on the sidewalls of the polysilicon lines before the photoresist layer is removed, the offset spacers can protect the polysilicon lines from being broken.

公开(公告)号：US6103606A

公开(公告)日：2000-08-15

申请号：US727089

申请日：1996-10-07

申请人： Der-Yuan Wu ,  Yi-Chung Sheng

发明人： Der-Yuan Wu ,  Yi-Chung Sheng

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/48 ,  H01L27/108

CPC分类号： H01L21/28061 ,  H01L21/76886

摘要： On a substrate with a number rows of gates are formed. After a metal silicide layer is formed above the gates, a silicon-rich layer is formed. The silicon-rich layer is either a further metal silicide layer, with a higher silicon concentration or a pure silicon layer.

摘要翻译： 在具有数排栅极的衬底上形成。 在栅极之上形成金属硅化物层之后，形成富硅层。 富硅层是另一金属硅化物层，具有较高的硅浓度或纯硅层。

公开(公告)号：US5504030A

公开(公告)日：1996-04-02

申请号：US505050

申请日：1995-07-21

申请人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

发明人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

IPC分类号： H01L21/8246

CPC分类号： H01L27/11246 ,  Y10S438/981

摘要： A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.

摘要翻译： 一种制造掩模ROM器件的存储单元的方法。 沿着第一方向延伸的多个源极/漏极区域通过将杂质注入构成存储器单元的位线的半导体衬底中而形成。 在通过液相沉积工艺由阻挡层限定的半导体衬底的指定区域上形成编码氧化物层，由此通过反复进行液相沉积工艺以形成一系列 编码具有增加的厚度的氧化物层。 在不被编码氧化物层覆盖的半导体衬底的一部分上形成栅氧化层。 栅极氧化物层的厚度小于编码氧化物层的厚度。 通过在构成所述存储单元的字线的编码氧化物层和栅极氧化物层上沉积和图案化导电层来形成沿着与第一方向正交的第二方向延伸的多个栅电极。 因此，每两个相邻位线和一个字线的横截面形成掩模ROM的存储单元，其中存储单元的阈值电压与栅极氧化物层和编码氧化物层的厚度成比例地变化。