公开(公告)号：US07531438B2

公开(公告)日：2009-05-12

申请号：US11491137

申请日：2006-07-24

申请人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

IPC分类号： H01L21/3205

CPC分类号： H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78 ,  Y10S438/981

摘要： A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

摘要翻译： 提供一种制造凹槽通道晶体管的方法。 首先，在掺杂半导体层和基板上形成硬掩模。 蚀刻掺杂半导体层和衬底以形成沟槽并且在掺杂半导体层中限定源极/漏极。 在沟槽的侧壁上以倾斜角度执行植入工艺以形成植入区域。 进行热氧化处理以形成氧化物层。 氧化物层包括在沟槽的侧壁中的源极/漏极上的第一厚度和在沟槽的侧壁中的另一部分上的第二厚度。

公开(公告)号：US06228730B1

公开(公告)日：2001-05-08

申请号：US09301211

申请日：1999-04-28

申请人： Tung-Po Chen ,  Jih-Wen Chou

发明人： Tung-Po Chen ,  Jih-Wen Chou

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7834

摘要： A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

摘要翻译： 一种制造场效应晶体管的方法，其中提供具有栅极的基板。 衬套氧化物层和第一间隔件邻近栅极的侧面形成。 在衬底的栅极的两侧形成外延硅层，而在外延硅层下面的衬底中形成浅源极/漏极（S / D）延伸结。 形成氧化物层和第二间隔物以紧密地连接到第一间隔物并在外延硅层下面形成S / D区。 然后将外延硅层的一部分转变成金属硅化物层，以完成场效应晶体管的工艺。

公开(公告)号：US06200870B1

公开(公告)日：2001-03-13

申请号：US09189355

申请日：1998-11-09

申请人： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

发明人： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28061 ,  H01L21/28247

摘要： A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.

摘要翻译： 用于形成提高栅极质量的栅极的方法包括在衬底上顺序地形成栅极氧化物层，多晶硅层，导电层和掩模层。 此后，对掩模层，导电层，多晶硅层和栅极氧化物层进行图案化以形成栅极。 然后，通过用氮阳离子的离子注入，在导电层的侧壁上形成用于增加栅极的热稳定性和化学稳定性的钝化层。 氮阳离子通过离子注入在栅极氧化物层下方掺杂到衬底中，这可以改善磷离子的渗透。

公开(公告)号：US06174791B1

公开(公告)日：2001-01-16

申请号：US09276294

申请日：1999-03-25

申请人： Tony Lin ,  Jih-Wen Chou ,  C. C. Hsue

发明人： Tony Lin ,  Jih-Wen Chou ,  C. C. Hsue

IPC分类号： H01L21425

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L29/665

摘要： A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.

摘要翻译： 一种用于在MOS晶体管的端子上形成非晶硅层的方法。 该方法包括以下步骤：形成具有在MOS晶体管上暴露栅极多晶硅层的开口的掩模层。 接下来，使用掩模层作为掩模，执行非活性离子注入操作，使得非活性离子注入到栅极多晶硅层中。 此后，再次使用掩模层作为掩模，进行第一次重轰击操作，局部注入离子。 最后，去除掩模层，然后进行第二次重轰击操作，全局注入离子。

公开(公告)号：US06165857A

公开(公告)日：2000-12-26

申请号：US469008

申请日：1999-12-21

申请人： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

发明人： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/417

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer. Next, the first dielectric layer is etched until upper surface of the gate and a portion of the substrate are exposed, wherein a part of the second dielectric layer is also etched accompanying with etching a part of the first dielectric layer. Further, second ions are implanted into the exposed substrate to form a source/drain region. A conductive layer is selectively formed on said over the exposed gate and source/drain. Finally, a self-aligned silicide layer is formed over the conductive layer.

摘要翻译： 公开了选择性外延生长的新改进。 在一个实施例中，本发明提供一种包括衬底的低功率金属氧化物半导体场效应晶体管（MOSFET）。 接着，在基板上形成栅极氧化层。 此外，在栅极氧化物层上沉积多晶硅层。 图案化以蚀刻多晶硅层和栅极氧化物层以限定栅极。 通过使用所述栅极作为硬掩模将第一离子注入到衬底中。 接下来，衬垫氧化物覆盖在所得结构的整个暴露表面上。 此外，适形的第一介电层和第二介电层以适当的顺序沉积在衬垫氧化物的上方。 回蚀第二电介质层以在第一电介质层的侧壁上形成电介质间隔物。 接下来，蚀刻第一电介质层直到栅极的上表面和衬底的一部分被暴露，其中第二电介质层的一部分也被蚀刻，同时蚀刻第一介电层的一部分。 此外，将第二离子注入暴露的衬底中以形成源/漏区。 在暴露的栅极和源极/漏极上的选择性地形成导电层。 最后，在导电层上形成自对准的硅化物层。

公开(公告)号：US5962900A

公开(公告)日：1999-10-05

申请号：US909726

申请日：1997-08-12

申请人： Jih-Wen Chou ,  Jemmy Wen

发明人： Jih-Wen Chou ,  Jemmy Wen

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L29/40 ,  H01L29/41

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/926

摘要： A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device. The feature size of the ROM device is thus dependent on the capability of the photolithographic process. The integration of the ROM device is thus high. The output division includes a plurality of MOSFETs whose gates are coupled to the memory cells in such a manner that the binary data can be read out by detecting the currents in the source/drain regions of these MOSFETs.

摘要翻译： 一种只读存储器（ROM）器件，其类型包括用于永久存储二进制编码数据的基于二极管的存储器单元阵列。 ROM设备被划分为存储器部分和输出部分。 存储器单元形成在存储器分区中的绝缘层上。 绝缘层将存储器单元与下层衬底分离，从而可以防止其间发生的泄漏电流。 此外，编码过程是通过在所选位置形成接触窗而不是按照常规方法进行离子注入而进行的。 因此制造工艺容易执行。 由于存储器单元是基于二极管的而不是基于MOSFET的，所以可以防止通常发生在基于MOSFET的存储器单元中的穿透效应。 基于二极管的结构还允许ROM器件上的存储器单元的堆积密度取决于ROM器件中多晶硅层的线宽。 因此ROM器件的特征尺寸取决于光刻工艺的能力。 因此，ROM设备的集成度很高。 输出部分包括多个MOSFET，其栅极以这样的方式耦合到存储器单元，使得可以通过检测这些MOSFET的源极/漏极区域中的电流来读出二进制数据。

公开(公告)号：US5904540A

公开(公告)日：1999-05-18

申请号：US994987

申请日：1997-12-19

申请人： Yi-Chung Sheng ,  Jih-Wen Chou

发明人： Yi-Chung Sheng ,  Jih-Wen Chou

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A method for forming shallow trench isolation comprising the steps of providing a substrate having a mask layer formed thereon. Next, the mask layer is patterned to form a first trench in the substrate. Then, dielectric spacers are formed on the sidewalls of the first trench. After that, a second trench is formed in the substrate by an etching operation following the profile of the dielectric spacers. Next, a second dielectric layer is formed filling the second trench, wherein the second dielectric layer and the dielectric spacers are formed from different materials. Thereafter, the dielectric spacers are removed to form recess cavities, and then a filler material is deposited into the recess cavities. Subsequently, a gate oxide layer is formed over the filler material and the substrate. Finally, a polysilicon gate layer is formed over the gate oxide layer.

摘要翻译： 一种用于形成浅沟槽隔离的方法，包括以下步骤：提供其上形成有掩模层的衬底。 接下来，对掩模层进行图案化以在衬底中形成第一沟槽。 然后，在第一沟槽的侧壁上形成电介质间隔物。 之后，通过蚀刻操作在介质间隔物的轮廓之后，在衬底中形成第二沟槽。 接下来，形成填充第二沟槽的第二电介质层，其中第二电介质层和电介质间隔物由不同的材料形成。 此后，去除电介质间隔物以形成凹陷腔，然后将填充材料沉积到凹腔中。 接着，在填充材料和基板上形成栅氧化层。 最后，在栅极氧化物层上形成多晶硅栅极层。

公开(公告)号：US5861329A

公开(公告)日：1999-01-19

申请号：US764254

申请日：1996-12-12

申请人： Wen-Kuan Yeh ,  Coming Chen ,  Meng-Jin Tsai ,  Jih-Wen Chou

发明人： Wen-Kuan Yeh ,  Coming Chen ,  Meng-Jin Tsai ,  Jih-Wen Chou

IPC分类号： H01L21/28 ,  H01L21/318 ,  H01L21/336 ,  H01L29/49 ,  H01L21/265 ,  H01L21/31

CPC分类号： H01L29/6659 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/28176 ,  H01L21/3185 ,  H01L29/4983 ,  H01L29/6656

摘要： A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.

摘要翻译： 提供一种制造金属氧化物半导体（MOS）晶体管的方法。 该方法特别设计用于降低由热载流子引起的对MOS晶体管的劣化程度。 在制造过程中，对晶片施加等离子体处理，以便在覆盖栅极的晶片和在源极/漏极区上的轻掺杂扩散（LDD）区域上形成氮化硅薄层 MOS晶体管。 该氮化硅薄层作为阻止热载流子与栅极介电层交叉的阻挡层，从而可以极大地最小化由于与跨越栅极电介质层的热载流子导致的MOS晶体管的劣化。

公开(公告)号：US5825069A

公开(公告)日：1998-10-20

申请号：US851545

申请日：1997-05-05

申请人： Jemmy Wen ,  Jih-Wen Chou

发明人： Jemmy Wen ,  Jih-Wen Chou

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L21/8246

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/91

摘要： A ROM device of the type including an array of diode-type memory cells and a method for fabricating the same are provided. The bit lines of this ROM device are a plurality of diffusion regions formed in an alternate manner on the bottom of a plurality of parallel-spaced trenches and on the top of the solid portions between these trenches. This particular arrangement of the bit lines allows for an increased integration of the diode-type memory cells on a limited wafer surface without having to reduce the feature size of the semiconductor components of the ROM device. The diode-type memory cells that are set to a permanently-ON state involve a P-N junction diode being formed therein, wherein the P-N junction diode is electrically connected via a contact window in an insulating layer to the associated one of the overlaying word lines. Other memory cells that are set to a permanently-OFF state are formed with no P-N junction diode therein.

摘要翻译： 提供了包括二极管型存储单元阵列的ROM器件及其制造方法。 该ROM器件的位线是在多个平行隔开的沟槽的底部上并且在这些沟槽之间的固体部分的顶部上以交替的方式形成的多个扩散区域。 位线的这种特定布置允许二极管型存储器单元在有限的晶片表面上的增加的集成，而不必减小ROM器件的半导体部件的特征尺寸。 设置为永久导通状态的二极管型存储单元包括在其中形成的P-N结二极管，其中P-N结二极管经由绝缘层中的接触窗口电连接到相关联的一个覆盖字线。 被设置为永久关闭状态的其他存储单元形成为没有P-N结二极管。

公开(公告)号：US20080233706A1

公开(公告)日：2008-09-25

申请号：US12111980

申请日：2008-04-30

申请人： Jih-Wen Chou ,  Yu-Chi Chen

发明人： Jih-Wen Chou ,  Yu-Chi Chen

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/10867 ,  H01L29/945

摘要： A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.

摘要翻译： 提供了动态随机存取存储器（DRAM）。 动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层， 门结构。 第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。 设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。 栅极结构设置在基板上。 栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。