公开(公告)号：US20130155381A1

公开(公告)日：2013-06-20

申请号：US13328278

申请日：2011-12-16

Applicant: Ya Hui Chang ,  Chia-Chu Liu

Inventor： Ya Hui Chang ,  Chia-Chu Liu

IPC: G03B27/32

CPC classification number: G03F7/2022 ,  G03F7/0045 ,  G03F7/095 ,  G03F7/2004 ,  G03F7/203 ,  G03F7/32 ,  H01L21/0274

Abstract: A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.

Abstract translation: 描述了在基板上形成图案的方法。 该方法包括提供衬底，在衬底上形成感光层，将感光层暴露于通过第一掩模的第一曝光能量，将感光层暴露于通过第二掩模的第二曝光能量，烘烤感光层和显影 曝光的感光层。 感光层包括使可溶于显影剂溶液的聚合物，至少一种光酸产生剂（PAG）和至少一种光产生剂（PBG）。 暴露于第二曝光能量的层的一部分与暴露于第一曝光能量的部分重叠。

公开(公告)号：US08877598B2

公开(公告)日：2014-11-04

申请号：US13486050

申请日：2012-06-01

Applicant: Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Ya Hui Chang ,  Kuei-Shun Chen

Inventor： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Ya Hui Chang ,  Kuei-Shun Chen

IPC: H01L21/336 ,  H01L21/4763 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/0271 ,  H01L21/2652 ,  H01L21/31144 ,  H01L27/1292 ,  H01L29/6659

Abstract: A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.

Abstract translation: 一种形成集成电路图案的方法。 该方法包括在衬底上形成栅极堆叠，门堆叠的两个相邻栅堆叠被尺寸G间隔开; 在栅叠层和衬底上形成含氮层; 在所述含氮层上形成介电材料层，所述电介质材料层的厚度T大致小于G / 2; 在介电材料层上涂覆光致抗蚀剂层; 并通过光刻工艺图案化光致抗蚀剂层。

公开(公告)号：US08592137B2

公开(公告)日：2013-11-26

申请号：US13328278

申请日：2011-12-16

Applicant: Ya Hui Chang ,  Chia-Chu Liu

Inventor： Ya Hui Chang ,  Chia-Chu Liu

IPC: G03F7/20

CPC classification number: G03F7/2022 ,  G03F7/0045 ,  G03F7/095 ,  G03F7/2004 ,  G03F7/203 ,  G03F7/32 ,  H01L21/0274

Abstract: A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.

公开(公告)号：US20130323898A1

公开(公告)日：2013-12-05

申请号：US13486050

申请日：2012-06-01

Applicant: Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Ya Hui Chang ,  Kuei-Shun Chen

Inventor： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Ya Hui Chang ,  Kuei-Shun Chen

IPC: H01L21/28 ,  H01L21/336

CPC classification number: H01L29/78606 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/0271 ,  H01L21/2652 ,  H01L21/31144 ,  H01L27/1292 ,  H01L29/6659

Abstract: A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.

Abstract translation: 一种形成集成电路图案的方法。 该方法包括在衬底上形成栅极堆叠，门堆叠的两个相邻栅堆叠被尺寸G间隔开; 在栅叠层和衬底上形成含氮层; 在所述含氮层上形成介电材料层，所述电介质材料层的厚度T大致小于G / 2; 在介电材料层上涂覆光致抗蚀剂层; 并通过光刻工艺图案化光致抗蚀剂层。

公开(公告)号：US08563410B2

公开(公告)日：2013-10-22

申请号：US12625957

申请日：2009-11-25

Applicant: Li-Te S. Lin ,  Meng Jun Wang ,  Ya Hui Chang ,  Hui Ouyang

Inventor： Li-Te S. Lin ,  Meng Jun Wang ,  Ya Hui Chang ,  Hui Ouyang

IPC: H01L21/3205

CPC classification number: H01L21/28026 ,  H01L21/28008 ,  H01L21/28123 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.

公开(公告)号：US20110124134A1

公开(公告)日：2011-05-26

申请号：US12625957

申请日：2009-11-25

Applicant: Li-Te S. Lin ,  Meng Jun Wang ,  Ya Hui Chang ,  Hui Ouyang

Inventor： Li-Te S. Lin ,  Meng Jun Wang ,  Ya Hui Chang ,  Hui Ouyang

IPC: H01L21/66 ,  H01L21/302

CPC classification number: H01L21/28026 ,  H01L21/28008 ,  H01L21/28123 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括在衬底上形成至少一个材料层; 执行端切割图案化工艺以形成覆盖所述至少一个材料层的端部切割图案; 将所述切割图案转印到所述至少一个材料层; 在切割图案化工艺之后进行线切割图案化工艺以形成覆盖至少一个材料层的线切割图案; 以及将所述切线图案转移到所述至少一个材料层。

公开(公告)号：US08730473B2

公开(公告)日：2014-05-20

申请号：US12892403

申请日：2010-09-28

Applicant: Ming-Feng Shieh ,  Ya Hui Chang ,  Ru-Gun Liu ,  Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Burn Jeng Lin

Inventor： Ming-Feng Shieh ,  Ya Hui Chang ,  Ru-Gun Liu ,  Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Burn Jeng Lin

IPC: G01B11/00 ,  H01L21/76 ,  H01L23/58

CPC classification number: H01L23/544 ,  G03F1/42 ,  G03F9/7076 ,  H01L21/0337 ,  H01L21/0338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

Abstract translation: 提供具有多个次分辨率元素的对准标记。 子分辨率元素各自具有小于可由对准过程中使用的对准信号检测的最小分辨率的维度。 还提供了其上形成有第一，第二和第三图案的半导体晶片。 第一和第二图案在第一方向上延伸，并且第三图案沿垂直于第一方向的第二方向延伸。 第二图案与第一图案分离在第二方向上测量的第一距离。 第三图案与第一图案分离在第一方向上测量的第二距离。 第三图案与第二图案分离在第一方向上测量的第三距离。 第一距离近似等于第三距离。 第二距离小于第一距离的两倍。

公开(公告)号：US20080131790A1

公开(公告)日：2008-06-05

申请号：US11565743

申请日：2006-12-01

Applicant: Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

Inventor： Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

IPC: G03F1/00 ,  G03F7/26

CPC classification number: G03F1/32 ,  G03F1/36

Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.

Abstract translation: 本公开提供了一种掩模。 掩模包括基底; 设置在所述基板上的第一衰减层，具有对应于相移的第一材料和第一厚度; 以及具有第二材料并设置在第一衰减层上的第二衰减层。 第一和第二衰减层限定第一特征，其具有延伸穿过第一和第二衰减层的第一开口; 以及具有延伸穿过第二衰减层并暴露第一衰减层的第二开口的第二特征。 第一和第二特征之一是主要特征，另一个是靠近主要特征的辅助功能。

公开(公告)号：US20130175629A1

公开(公告)日：2013-07-11

申请号：US13343771

申请日：2012-01-05

Applicant: Ya Hui Chang

Inventor： Ya Hui Chang

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L21/28 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823475

Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.

Abstract translation: 公开了一种用于小沟槽图案化的半导体器件和方法。 该器件包括多个栅极结构和侧壁间隔物，设置在侧壁间隔物上的蚀刻停止层，设置在蚀刻停止层的底部上的层间电介质层（ILD）层，设置在蚀刻停止层的上部的蚀刻缓冲层 蚀刻停止层以及栅极结构之间的多个金属插塞。 金属塞的上部与蚀刻缓冲层相邻，并且金属塞的下部与ILD层相邻。

公开(公告)号：US07838173B2

公开(公告)日：2010-11-23

申请号：US11565743

申请日：2006-12-01

Applicant: Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

Inventor： Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

IPC: G03F1/00 ,  H01L21/00

CPC classification number: G03F1/32 ,  G03F1/36

Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.

Abstract translation: 本公开提供了一种掩模。 掩模包括基底; 设置在所述基板上的第一衰减层，具有对应于相移的第一材料和第一厚度; 以及具有第二材料并设置在第一衰减层上的第二衰减层。 第一和第二衰减层限定第一特征，其具有延伸穿过第一和第二衰减层的第一开口; 以及具有延伸穿过第二衰减层并暴露第一衰减层的第二开口的第二特征。 第一和第二特征之一是主要特征，另一个是靠近主要特征的辅助功能。