公开(公告)号：US08703392B2

公开(公告)日：2014-04-22

申请号：US13602445

申请日：2012-09-04

申请人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

发明人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

IPC分类号： G03F7/26 ,  B05B7/00 ,  B05C11/00

CPC分类号： G03F7/322

摘要： The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.

摘要翻译： 本公开涉及制造半导体器件的方法。 该方法包括提供其上形成有材料层的基板; 在所述材料层上沉积光致抗蚀剂层，所述光致抗蚀剂层具有垂直尺寸; 将所述光致抗蚀剂层的区域暴露于辐射，所述暴露区域具有水平尺寸，其中所述垂直尺寸与所述水平尺寸的第一比例超过预定比率; 并且通过施加包含第一化学品和第二化学品的显影剂溶液，至少部分地显影所述光致抗蚀剂层以去除所述暴露区域，其中：所述第一化学品被配置为通过化学反应溶解所述光致抗蚀剂层的暴露区域; 第二化学品被配置为增强与光致抗蚀剂层接触的第一化学品的流动; 并且在第一化学品和第二化学品之间存在优化的第二比例。

公开(公告)号：US20140065554A1

公开(公告)日：2014-03-06

申请号：US13602445

申请日：2012-09-04

申请人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

发明人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

IPC分类号： G03F7/20 ,  G03B27/32

CPC分类号： G03F7/322

摘要： The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.

摘要翻译： 本公开涉及制造半导体器件的方法。 该方法包括提供其上形成有材料层的基板; 在所述材料层上沉积光致抗蚀剂层，所述光致抗蚀剂层具有垂直尺寸; 将所述光致抗蚀剂层的区域暴露于辐射，所述暴露区域具有水平尺寸，其中所述垂直尺寸与所述水平尺寸的第一比例超过预定比率; 并且通过施加包含第一化学品和第二化学品的显影剂溶液，至少部分地显影所述光致抗蚀剂层以去除所述暴露区域，其中：所述第一化学品被配置为通过化学反应溶解所述光致抗蚀剂层的暴露区域; 第二化学品被配置为增强与光致抗蚀剂层接触的第一化学品的流动; 并且在第一化学品和第二化学品之间存在优化的第二比例。

公开(公告)号：US20130323898A1

公开(公告)日：2013-12-05

申请号：US13486050

申请日：2012-06-01

申请人： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Ya Hui Chang ,  Kuei-Shun Chen

发明人： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Ya Hui Chang ,  Kuei-Shun Chen

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/78606 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/0271 ,  H01L21/2652 ,  H01L21/31144 ,  H01L27/1292 ,  H01L29/6659

摘要： A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.

摘要翻译： 一种形成集成电路图案的方法。 该方法包括在衬底上形成栅极堆叠，门堆叠的两个相邻栅堆叠被尺寸G间隔开; 在栅叠层和衬底上形成含氮层; 在所述含氮层上形成介电材料层，所述电介质材料层的厚度T大致小于G / 2; 在介电材料层上涂覆光致抗蚀剂层; 并通过光刻工艺图案化光致抗蚀剂层。

公开(公告)号：US07915105B2

公开(公告)日：2011-03-29

申请号：US12431838

申请日：2009-04-29

申请人： Matt Yeh ,  Shun Wu Lin ,  Chung-Ming Wang ,  Chi-Chun Chen

发明人： Matt Yeh ,  Shun Wu Lin ,  Chung-Ming Wang ,  Chi-Chun Chen

IPC分类号： H01L21/338 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/0207 ,  H01L29/66545

摘要： The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.

摘要翻译： 本公开提供了一种用于制造半导体器件的方法。 该方法包括在半导体衬底上形成第一，第二，第三和第四栅极结构，每个栅极结构具有虚拟栅极，从第一，第二，第三和第四栅极结构去除伪栅极，从而形成第一， 第三沟槽和第四沟槽，分别形成金属层以部分地填充在第一，第二，第三和第四沟槽中，在第一，第二和第三沟槽上形成第一光致抗蚀剂层，蚀刻金属层的一部分 第四沟槽，去除第一光致抗蚀剂层，在第二和第三沟槽上形成第二光致抗蚀剂层，蚀刻第一沟槽中的金属层和第四沟槽中金属层的剩余部分，以及去除第二光致抗蚀剂层。

公开(公告)号：US20100086875A1

公开(公告)日：2010-04-08

申请号：US12285466

申请日：2008-10-06

申请人： Chung-Ming Wang ,  Steven Maxwell ,  Paul Wai Kie Poon ,  Yung-Tin Chen

发明人： Chung-Ming Wang ,  Steven Maxwell ,  Paul Wai Kie Poon ,  Yung-Tin Chen

IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/033

CPC分类号： H01L21/0334 ,  H01L21/0338

摘要： A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.

摘要翻译： 一种制造器件的方法包括在下面的层上形成下面的掩模层，在下面的掩模层之上形成第一掩模层，对第一掩模层进行图案化以形成第一掩模特征，利用下面的掩模层来切割下面的掩模特征，使用 第一掩模作为掩模，去除第一掩模特征，并使用至少底层掩模特征作为掩模来图案化底层。

公开(公告)号：US20050208814A1

公开(公告)日：2005-09-22

申请号：US11053886

申请日：2005-02-10

申请人： Kun-Shiang Tsai ,  Chung-Ming Wang

发明人： Kun-Shiang Tsai ,  Chung-Ming Wang

IPC分类号： H01R4/50 ,  H01R13/24 ,  H01R13/62 ,  H04B1/38 ,  H04M1/02

CPC分类号： H04B1/3818 ,  G06K13/0862 ,  H01R4/5066 ,  H01R13/24

摘要： A cover comprises a first guide portion and a second guide portion. A side surface of the cover pivots to a case. When the cover closes, the cover mantles a moving component in a container of the case. The first guide portion is adjacent to a first side surface. When the cover opens, the first guide portion pushes the moving component to depart from a specific position in the container. The second guide portion is adjacent to a second side surface of the cover. When the cover closes, the second guide portion pushes the moving component to the specific position in the container. Moreover, in an electrical apparatus, a moving component is placed in a container thereof. The electrical apparatus includes a cover and a case in which the container is disposed. The cover has a side surface pivoting to the case. When the cover closes, the cover mantles the moving component in the container.

摘要翻译： 盖包括第一引导部分和第二引导部分。 盖的侧表面枢转到壳体。 当盖关闭时，盖罩将壳体的容器中的移动部件套住。 第一引导部分与第一侧表面相邻。 当盖打开时，第一引导部分推动移动部件离开容器中的特定位置。 第二引导部分与盖的第二侧表面相邻。 当盖关闭时，第二引导部分将移动部件推动到容器中的特定位置。 此外，在电气设备中，将移动部件放置在其容器中。 电气设备包括盖子和容器设置的壳体。 盖子有一个侧面可旋转到外壳。 当盖关闭时，盖子将容器中的移动部件套住。

公开(公告)号：US08765363B2

公开(公告)日：2014-07-01

申请号：US13478559

申请日：2012-05-23

申请人： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen

发明人： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen

IPC分类号： G03F7/38

CPC分类号： G03F7/38 ,  G03F7/09 ,  H01L21/0274 ,  H01L21/76224

摘要： A method of forming a integrated circuit pattern. The method includes coating a photoresist layer on a substrate; performing a lithography exposure process to the photoresist layer; performing a multiple-step post-exposure-baking (PEB) process to the photoresist layer; and developing the photoresist layer to form a patterned photoresist layer.

摘要翻译： 一种形成集成电路图案的方法。 该方法包括在基底上涂覆光致抗蚀剂层; 对光致抗蚀剂层进行光刻曝光工艺; 对光致抗蚀剂层进行多步曝光后烘烤（PEB）处理; 并且显影光致抗蚀剂层以形成图案化的光致抗蚀剂层。

公开(公告)号：US20130316510A1

公开(公告)日：2013-11-28

申请号：US13478559

申请日：2012-05-23

申请人： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen

发明人： Chung-Ming Wang ,  Yu Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen

IPC分类号： H01L21/336 ,  H01L21/302 ,  G03F7/20

CPC分类号： G03F7/38 ,  G03F7/09 ,  H01L21/0274 ,  H01L21/76224

摘要： A method of forming a integrated circuit pattern. The method includes coating a photoresist layer on a substrate; performing a lithography exposure process to the photoresist layer; performing a multiple-step post-exposure-baking (PEB) process to the photoresist layer; and developing the photoresist layer to form a patterned photoresist layer.

摘要翻译： 一种形成集成电路图案的方法。 该方法包括在基底上涂覆光致抗蚀剂层; 对光致抗蚀剂层进行光刻曝光工艺; 对光致抗蚀剂层进行多步曝光后烘烤（PEB）处理; 并且显影光致抗蚀剂层以形成图案化的光致抗蚀剂层。

公开(公告)号：US20100112811A1

公开(公告)日：2010-05-06

申请号：US12431838

申请日：2009-04-29

申请人： Matt Yeh ,  Shun Wu Lin ,  Chung-Ming Wang ,  Chi-Chun Chen

发明人： Matt Yeh ,  Shun Wu Lin ,  Chung-Ming Wang ,  Chi-Chun Chen

IPC分类号： H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/0207 ,  H01L29/66545

摘要： The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.

摘要翻译： 本公开提供了一种用于制造半导体器件的方法。 该方法包括在半导体衬底上形成第一，第二，第三和第四栅极结构，每个栅极结构具有虚拟栅极，从第一，第二，第三和第四栅极结构去除伪栅极，从而形成第一， 第三沟槽和第四沟槽，分别形成金属层以部分地填充在第一，第二，第三和第四沟槽中，在第一，第二和第三沟槽上形成第一光致抗蚀剂层，蚀刻金属层的一部分 第四沟槽，去除第一光致抗蚀剂层，在第二和第三沟槽上形成第二光致抗蚀剂层，蚀刻第一沟槽中的金属层和第四沟槽中金属层的剩余部分，以及去除第二光致抗蚀剂层。

公开(公告)号：US07530747B2

公开(公告)日：2009-05-12

申请号：US11340635

申请日：2006-01-27

申请人： Chung-Ming Wang ,  Kun-Shiang Tsai

发明人： Chung-Ming Wang ,  Kun-Shiang Tsai

IPC分类号： G03B17/00 ,  G02B27/02 ,  G02B7/18

CPC分类号： H04M1/0264 ,  H04B1/3888 ,  H04N5/2252 ,  H04N5/2257

摘要： A mobile device having a digital camera and an assembling method for a ring is disclosed. The mobile device includes a housing, a digital camera module and the ring, wherein the housing has a through hole which a notch is formed therein. The digital camera module has an arm. The ring is disposed in the through hole. Besides, one side of the ring includes an extended part which is located on the notch and forms a dynamic relationship with the arm.

摘要翻译： 公开了一种具有数字照相机和环的组装方法的移动设备。 移动装置包括壳体，数字照相机模块和环，其中壳体具有在其中形成有凹口的通孔。 数码相机模块有一个臂。 环设置在通孔中。 此外，环的一侧包括位于凹口上并与臂形成动态关系的延伸部分。