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公开(公告)号：US20240194276A1
公开(公告)日：2024-06-13
申请号：US18326750
申请日：2023-05-31
发明人： Teng CHEN , Liang QIAO , Masao KURIYAMA
IPC分类号： G11C16/34
CPC分类号： G11C16/3459
摘要： Aspects of the present disclosure provide a memory, a control method thereof, and a memory system. The memory includes a memory cell array and a peripheral circuit, the peripheral circuit comprising at least a trigger circuit comprising a reference signal output circuit and a fail bit signal output circuit, wherein the fail bit signal output circuit is configured to generate a fail bit signal according to a test signal obtained from verification of the memory, and the reference signal output circuit is configured to output a plurality of reference signals; and a comparator coupled with the trigger circuit and configured to compare the fail bit signal with the at least one reference signal to output a verification result.
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公开(公告)号：US20240296894A1
公开(公告)日：2024-09-05
申请号：US18663879
申请日：2024-05-14
发明人： Weiwei HE , Liang QIAO , Mingxian LEI
IPC分类号： G11C16/16 , G11C7/08 , G11C16/04 , G11C16/26 , H03K19/017
CPC分类号： G11C16/16 , G11C7/08 , G11C16/0433 , G11C16/26 , H03K19/01742
摘要： A method of operating a memory device is disclosed. The memory device includes a memory string coupled with a bit line and a common source line. An erase voltage is applied to the bit line and the common source line in an erase operation. The bit line and the common source line are discharged in a discharge operation after the erase operation. A voltage difference between the bit line and the common source line is less than a first predetermined value during a period of the discharge operation.
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3.发明公开公开(公告)号：US20240153544A1
公开(公告)日：2024-05-09
申请号：US18412873
申请日：2024-01-15
发明人： Liang QIAO
CPC分类号： G11C7/12 , G11C16/0483 , G11C16/24 , H03K19/1737
摘要： A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit coupled between the current control circuit and a ground. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. First terminals of the first transistors each is in connection with one of the bit lines. Second terminals of the first transistors each is in connection with the discharge enable circuit. Third terminals of the first transistors are in connection with a reference current generator of the current control circuit.
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公开(公告)号：US20240005994A1
公开(公告)日：2024-01-04
申请号：US18147537
申请日：2022-12-28
发明人： Liang QIAO , Bowen WANG
CPC分类号： G11C16/10 , G11C16/08 , G11C16/24 , G11C16/0483
摘要： The present application discloses a memory device, a programming method and a memory system. The memory device comprises: a memory cell array comprising a plurality of word lines and a plurality of bit lines; each of the word lines comprising at least two word line segments; each of the word line segment in the word line having different signal transmission distances from a word line driver; different word line segments in the word line corresponding to different bit lines respectively; the word line driver configured to apply a word line voltage to the word line; a bit line driver configured to apply different bias voltages to different bit lines corresponding to the different word line segments respectively during application of a programming pulse.
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公开(公告)号：US20230268008A1
公开(公告)日：2023-08-24
申请号：US17847657
申请日：2022-06-23
发明人： Weiwei HE , Liang QIAO , Mingxian LEI
IPC分类号： G11C16/16 , G11C16/26 , G11C16/04 , G11C7/08 , H03K19/017
CPC分类号： G11C16/16 , G11C16/26 , G11C16/0433 , G11C7/08 , H03K19/01742
摘要： The present disclosure provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.
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公开(公告)号：US20240221842A1
公开(公告)日：2024-07-04
申请号：US18330120
申请日：2023-06-06
发明人： Yi CAO , Ke LIANG , Liang QIAO
CPC分类号： G11C16/24 , G11C16/0483
摘要： Devices, systems, and methods for counting a quantity of fail-bits in a memory device using a VFC circuit are disclosed. The VFC circuit can be calibrated via an offset adjustment mechanism to compensate an internal mismatch. The VFC circuit can include a processing unit and a circuit coupled to the processing unit. The processing unit can receive a first signal representing a number of detected fail-bits in the memory array, process the first signal and an offset signal, and generate a second signal representing a quantity of fail-bits. The circuit can receive the first and second signals, determine a difference between the quantity of fail-bits represented by the second signal and the number of detected fail-bits represented by the first signal, adjust the offset signal according to the difference, and provide the offset signal to the processing unit.
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公开(公告)号：US20220319570A1
公开(公告)日：2022-10-06
申请号：US17307924
申请日：2021-05-04
发明人： Liang QIAO
IPC分类号： G11C11/4074 , G11C11/4099 , G11C11/4094 , G11C11/4076 , G11C11/4093 , H03K19/173
摘要： A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. The current control circuit is coupled to the plurality of bit lines to control a discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges a charge on the plurality of bit lines.
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