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    Method to detect blocker signals in interleaved analog-to-digital converters
    1.
    发明授权
    Method to detect blocker signals in interleaved analog-to-digital converters 有权

    公开(公告)号：US10218372B1

    公开(公告)日：2019-02-26

    申请号：US15939257

    申请日：2018-03-28

    Applicant: Xilinx, Inc.

    Inventor： Brendan Farley ,  Christophe Erdmann ,  John E. McGrath ,  Bruno Miguel Vaz

    IPC: H03M1/10

    Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.

    Latency synchronization across clock domains
    2.
    发明授权
    Latency synchronization across clock domains 有权

    公开(公告)号：US10969821B2

    公开(公告)日：2021-04-06

    申请号：US15991179

    申请日：2018-05-29

    Applicant: Xilinx, Inc.

    Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

    IPC: G06F1/12 ,  G06F1/14 ,  G06F1/10

    Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

    Phase coherent and frequency hopping numerically controlled oscillator
    3.
    发明授权
    Phase coherent and frequency hopping numerically controlled oscillator 有权

    公开(公告)号：US10917077B1

    公开(公告)日：2021-02-09

    申请号：US16694485

    申请日：2019-11-25

    Applicant: Xilinx, Inc.

    Inventor： Ali Boumaalif ,  John E. McGrath

    IPC: G06F1/03 ,  H03C3/00 ,  H03K5/00 ,  H03K4/08

    Abstract: A device includes a plurality of phase accumulators, a multiplexer, and an oscillator. The plurality of phase accumulators is configured to receive a plurality of frequencies and generate a plurality of ramp signals. The multiplexer is configured to receive the plurality of ramp signals from the plurality of phase accumulators and to select one ramp signal from the plurality of ramp signals. The oscillator is configured to receive the one selected ramp signal and to generate one amplitude signal associated therewith. The plurality of phase accumulators continues generating their respective ramp signal. The multiplexer subsequent to selecting the one ramp signal is configured to select another ramp signal associated with another one phase accumulator of the plurality of phase accumulators. The oscillator is further configured to receive the selected another ramp signal and to generate another amplitude signal associated therewith.

    LATENCY SYNCHRONIZATION ACROSS CLOCK DOMAINS
    4.
    发明申请
    LATENCY SYNCHRONIZATION ACROSS CLOCK DOMAINS 审中-公开

    公开(公告)号：US20200097038A1

    公开(公告)日：2020-03-26

    申请号：US15991179

    申请日：2018-05-29

    Applicant: Xilinx, Inc.

    Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

    IPC: G06F1/12 ,  G06F1/10 ,  G06F1/14

    Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

    Reconfiguration of single-band transmit and receive paths to multi-band transmit and receive paths in an integrated circuit
    6.
    发明授权
    Reconfiguration of single-band transmit and receive paths to multi-band transmit and receive paths in an integrated circuit 有权

    公开(公告)号：US09847802B1

    公开(公告)日：2017-12-19

    申请号：US15238537

    申请日：2016-08-16

    Applicant: Xilinx, Inc.

    Inventor： Brendan Farley ,  John E. McGrath

    IPC: H04K1/10 ,  H04L27/28 ,  H04B1/04 ,  H04B1/16

    CPC classification number: H04B1/0483 ,  H04B1/005 ,  H04B1/16 ,  H04B1/406

    Abstract: An example transmitter includes first and second circuit stages and interface circuits. The first circuit stage is configured to generate modulated signals each having a different carrier frequency from baseband signals. The second circuit stage is configured to generate radio frequency (RF) energy to be radiated by antenna(s). The interface circuits are coupled between the first circuit stage and the second circuit stage. The second circuit stage and the interface circuits are configurable to provide a first mode and a second mode. In the first mode, the second circuit stage provides transmit paths and the interface circuits couple each of the modulated signals to a respective one of the transmit paths. In the second mode, the second circuit stage provides a first transmit path and the interface circuits couple a sum of at least two of the modulated signals to the first transmit path.

    Dynamic capacitors for tuning of circuits
    9.
    发明授权
    Dynamic capacitors for tuning of circuits 有权
    用于调谐电路的动态电容器

    公开(公告)号：US09431812B1

    公开(公告)日：2016-08-30

    申请号：US13621942

    申请日：2012-09-18

    Applicant: Xilinx, Inc.

    Inventor： John E. McGrath

    IPC: G05F1/10 ,  H01H51/34 ,  H02G7/20 ,  B41J2/045

    CPC classification number: H02G7/20 ,  B41J2/04541 ,  H01L23/5223 ,  H01L23/5225

    Abstract: A circuit includes a signal line formed of at least one conductive element and a shield at least partially encompassing the signal line. The circuit further includes a first dynamic capacitor located between the shield and the signal line. The first dynamic capacitor is configured to provide a first variable amount of capacitance.

    Abstract translation: 电路包括由至少一个导电元件和至少部分地包围该信号线的屏蔽层形成的信号线。 电路还包括位于屏蔽和信号线之间的第一动态电容器。 第一动态电容器被配置为提供第一可变量的电容。

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