公开(公告)号：US11211901B1

公开(公告)日：2021-12-28

申请号：US17037378

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Vipul Bajaj ,  Bruno Miguel Vaz

IPC: H03F1/26 ,  H03F3/30 ,  H03F3/00 ,  H03F3/217

Abstract: An amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, and an output node. The first capacitor is electrically connected between a first power supply node and a first node, the second capacitor is electrically connected between the first node and a second node, the third capacitor is electrically connected between a second power supply node and a third node, and the fourth capacitor is electrically connected between the third node and a fourth node. The first transistor has a gate node electrically connected to the second node, and the second transistor has a gate node electrically connected to the fourth node. The output node is selectively connected to the first transistor and the second transistor. The first node and the third node are configured to be selectively electrically connected to a voltage node and a common voltage node.

公开(公告)号：US10218372B1

公开(公告)日：2019-02-26

申请号：US15939257

申请日：2018-03-28

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  Christophe Erdmann ,  John E. McGrath ,  Bruno Miguel Vaz

IPC: H03M1/10

Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.

公开(公告)号：US10476514B1

公开(公告)日：2019-11-12

申请号：US15992797

申请日：2018-05-30

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  John E. McGrath ,  Conrado K. Mesadri ,  Woon C. Wong ,  Ali Boumaalif ,  Christophe Erdmann ,  Brendan Farley

IPC: H03M1/12 ,  G01R31/3185 ,  H03M1/10 ,  H04L12/43 ,  H04L12/433

Abstract: An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

公开(公告)号：US10371725B1

公开(公告)日：2019-08-06

申请号：US15994060

申请日：2018-05-31

Applicant: Xilinx, Inc.

Inventor： Alonso Morgado ,  Bruno Miguel Vaz ,  Edward Cullen ,  Christophe Erdmann

IPC: G08B21/00 ,  G01R19/165 ,  H02H9/04 ,  H03K19/003

Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.

公开(公告)号：US10404265B1

公开(公告)日：2019-09-03

申请号：US16117650

申请日：2018-08-30

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  Bruno Miguel Vaz ,  Darragh Walsh

IPC: H03M1/80 ,  H03F3/30

Abstract: An example apparatus includes a first transistor coupled between a supply node and a first node, a current mirror having a first side and a second side, and a second transistor coupled between the first node and the first side of the current mirror. The input buffer further includes a third transistor coupled between the first node and the second side of the current mirror, and a first capacitor coupled between a source and a drain of the second transistor.

公开(公告)号：US10256802B1

公开(公告)日：2019-04-09

申请号：US15616872

申请日：2017-06-07

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz

IPC: H03K17/0812 ,  H03M1/12 ,  G01R19/165

Abstract: In an example, an input buffer includes: first buffer circuit having an output, a first voltage control node, and a second voltage control node; a first transistor having a gate coupled to the output of the first buffer circuit, a drain, and a source; a second buffer circuit having an input coupled to a reference voltage and an output coupled to the source of the first transistor; and a first current source having a reference output coupled to the drain of the first transistor, a first output coupled to the first voltage control node of the first buffer circuit, and a second output coupled to the second voltage control node of the second buffer circuit.

公开(公告)号：US10033395B1

公开(公告)日：2018-07-24

申请号：US15684900

申请日：2017-08-23

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz

IPC: H03M1/00 ,  H03M1/12

Abstract: An analog to digital converter (ADC) circuit includes a first stage for converting a first analog voltage signal to a first digital signal including a first portion of a digital output signal representing the first analog voltage signal, and generate a first residue voltage based on the first analog voltage signal and the first digital signal. A first amplifier control unit generates a first amplifier start signal based on a second stage ready signal indicating that a second stage is ready to process a second analog voltage signal. In response to the second stage ready signal, a first amplifier generates the second analog voltage signal based on the first residue voltage. The second stage is configured to generate the second stage ready signal, receive the second analog voltage signal, and convert the second analog voltage signal to a second digital signal including a second portion of the digital output signal.

公开(公告)号：US11218160B1

公开(公告)日：2022-01-04

申请号：US17037371

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Bruno Miguel Vaz ,  Vipul Bajaj

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/36

Abstract: An analog-to-digital (ADC) circuit is disclosed that includes a first stage, a first amplifier, and a second amplifier. The first stage includes signal processing circuitry, and is configured to receive a differential input signal and generate a differential residue voltage signal on differential output nodes of the first stage. The first amplifier includes first amplifier circuitry. The first amplifier is electrically connected to the differential output nodes of the first stage, and configured to receive the differential residue voltage signal, and generate a first differential voltage signal from the differential residue voltage signal. The second amplifier includes second amplifier circuitry. The second amplifier is electrically connected to differential output nodes of the first amplifier, and configured to receive the first differential voltage signal, and generate a second differential voltage signal from the first differential voltage signal.

公开(公告)号：US11183992B1

公开(公告)日：2021-11-23

申请号：US16852729

申请日：2020-04-20

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Bruno Miguel Vaz

IPC: H03K5/02 ,  H03K5/1252

Abstract: A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.

公开(公告)号：US10944414B1

公开(公告)日：2021-03-09

申请号：US16922873

申请日：2020-07-07

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/06

Abstract: An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.