DIFFERENTIABLE MODEL FOR MANUFACTURABILITY
    3.
    发明公开

    公开(公告)号:US20230251620A1

    公开(公告)日:2023-08-10

    申请号:US17665860

    申请日:2022-02-07

    CPC classification number: G05B19/188 G05B13/0265 G05B2219/45031

    Abstract: Systems, computer-implemented methods, and instructions encoded in machine-accessible storage media are provided for determining manufacturability of an integrated circuit layout. A computer-implemented method includes receiving a layout describing the integrated circuit to be manufactured by a semiconductor manufacturing process. The method also includes generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter. The differentiable manufacturability parameter describes the manufacturability of the integrated circuit by the semiconductor manufacturing process.

    Machine learning based layout nudging for design rule compliance

    公开(公告)号:US11675960B2

    公开(公告)日:2023-06-13

    申请号:US17516476

    申请日:2021-11-01

    CPC classification number: G06F30/398 G06F30/27 G06F30/323

    Abstract: Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.

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