公开(公告)号：US20240266348A1

公开(公告)日：2024-08-08

申请号：US18105586

申请日：2023-02-03

Applicant: Wolfspeed, Inc.

Inventor： Fabian Radulescu ,  Basim Noori ,  Scott Sheppard ,  Qianli Mu ,  Jeremy Fisher ,  Dan Namishia

IPC: H01L27/085 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L27/085 ,  H01L23/528 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/13014 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/16227

Abstract: A transistor device includes a substrate and a plurality of transistor unit cells arranged in parallel on the substrate. Each of the transistor unit cells includes a source contact, a drain contact, and a gate finger between the source contact and the drain contact. The gate finger extends in a first direction and has a first end and a second end. The transistor device further includes a first solder bump on the transistor device that is within a periphery of the active region of the device and is electrically connected to the gate finger of a first one of the unit cells at a feed point that is between the first end and the second end of the gate finger.

公开(公告)号：US20230215833A1

公开(公告)日：2023-07-06

申请号：US17567322

申请日：2022-01-03

Applicant: Wolfspeed, Inc.

Inventor： Dan Namishia ,  Mitch Flowers ,  Eng Wah Woo ,  Erwin Cohen

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/29 ,  H01L2924/1423 ,  H01L2224/32225 ,  H01L2924/10156 ,  H01L2924/13064 ,  H01L2924/1033 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2224/29139 ,  H01L24/48 ,  H01L2224/48225 ,  H01L24/73 ,  H01L2224/73265

Abstract: A semiconductor chip comprises a substrate, a die attach material, and a die. The substrate comprises an upper surface and a lower surface opposing the upper surface. The die attach material is on the upper surface of the substrate. The die comprises a bottom surface bonded to the upper surface of the substrate by the die attach material, a top surface opposing the bottom surface, and a side wall adjacent to the top surface and the bottom surface. A shortest distance across an exterior of the side wall from the bottom surface to the top surface defines an exterior surface distance. The die further comprises a die height measured from where the side wall meets the bottom surface to where the side wall meets the top surface. The exterior surface distance is longer than the die height.

公开(公告)号：US11616136B2

公开(公告)日：2023-03-28

申请号：US17180048

申请日：2021-02-19

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Evan Jones ,  Dan Namishia ,  Chris Hardiman ,  Fabian Radulescu ,  Terry Alcorn ,  Scott Sheppard ,  Bruce Schmukler

IPC: H01L21/00 ,  H01L29/08 ,  H01L29/778 ,  H01L21/285 ,  H01L21/306 ,  H01L21/765 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H03F1/02 ,  H03F3/21

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

公开(公告)号：US20240105763A1

公开(公告)日：2024-03-28

申请号：US17952267

申请日：2022-09-25

Applicant: Wolfspeed, Inc.

Inventor： Jeremy Fisher ,  Marvin Marbell ,  Dan Namishia ,  Dan Etter

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/7783 ,  H01L29/7787

Abstract: A device according to some embodiments includes a metal-insulator-metal (MIM) capacitor including a substrate, an upper metal plate, and a lower metal surface attached to a first surface of the substrate. The upper metal plate of the MIM capacitor is configured to serve as a wire bonding surface. Other embodiments include an RF transistor package and a device including a MIM capacitor that includes at least one via.

公开(公告)号：US20240072732A1

公开(公告)日：2024-02-29

申请号：US17900652

申请日：2022-08-31

Applicant: Wolfspeed, Inc.

Inventor： Donald Farrell ,  Dan Namishia ,  Kyle Bothe ,  Brad Millon

IPC: H03F1/02 ,  H01L23/66 ,  H03F1/56 ,  H03F3/195

CPC classification number: H03F1/0288 ,  H01L23/66 ,  H03F1/565 ,  H03F3/195 ,  H01L2223/6611 ,  H01L2223/6655 ,  H03F2200/451

Abstract: A transistor die includes a transistor including a control terminal, an output terminal, and a first partial matching circuit. The first partial matching circuit is connected to at least one of the control terminal of the transistor and the output terminal of the transistor, and is configured to tune an input impedance of the transistor die. A packaged device is also provided.

公开(公告)号：US20230291367A1

公开(公告)日：2023-09-14

申请号：US17688952

申请日：2022-03-08

Applicant: Wolfspeed, Inc.

Inventor： Jeremy Fisher ,  Dan Namishia ,  Scott Sheppard

IPC: H03F3/195 ,  H03F1/56 ,  H01L23/66

CPC classification number: H03F3/195 ,  H03F1/565 ,  H01L23/66 ,  H03F2200/451 ,  H01L2223/6655

Abstract: Semiconductor devices are provided that include a Group III nitride-based semiconductor layer structure. A first metal layer is formed on an upper surface of the semiconductor layer structure, a first dielectric layer is formed on an upper surface of the first metal layer, and a second metal layer is formed on an upper surface of the first dielectric layer. The first metal layer, the first dielectric layer and the second metal layer form a first capacitor. A second dielectric layer is formed on an upper surface of the second metal layer, a third dielectric layer is formed on an upper surface of the second dielectric layer, and a third metal layer is formed on upper surfaces of the second and third dielectric layers. The second metal layer, the second dielectric layer and the third metal layer form a second capacitor that is stacked on the first capacitor.

公开(公告)号：US11682634B2

公开(公告)日：2023-06-20

申请号：US17060540

申请日：2020-10-01

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Dan Namishia ,  Fabian Radulescu ,  Scott Sheppard

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/66 ,  H01L23/64 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/564 ,  H01L23/31 ,  H01L23/528 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6683

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

公开(公告)号：US11658234B2

公开(公告)日：2023-05-23

申请号：US17325576

申请日：2021-05-20

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Terry Alcorn ,  Dan Namishia ,  Jia Guo ,  Matt King ,  Saptharishi Sriram ,  Jeremy Fisher ,  Fabian Radulescu ,  Scott Sheppard ,  Yueying Liu

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/402 ,  H01L29/66462

Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ΓD. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ΓD is less than about 0.3 μm, and the distance d1 is less than about 80 nm.