公开(公告)号：US10355034B2

公开(公告)日：2019-07-16

申请号：US15578562

申请日：2017-10-13

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Tao Wang

IPC: H01L27/12 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.

公开(公告)号：US20190057986A1

公开(公告)日：2019-02-21

申请号：US15578562

申请日：2017-10-13

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Tao Wang

IPC: H01L27/12 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L27/1274 ,  H01L21/0243 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/2855 ,  H01L21/32133 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1262 ,  H01L29/66757 ,  H01L29/78672 ,  H01L29/78675

Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.

公开(公告)号：US10355138B2

公开(公告)日：2019-07-16

申请号：US15735614

申请日：2017-06-22

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Tao Wang

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/266 ,  H01L21/02 ,  H01L29/66 ,  H01L29/167 ,  H01L21/285 ,  H01L21/3213 ,  G02F1/1343 ,  H01L21/027 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1333

Abstract: A low temperature polysilicon (LTPS) thin film transistor (TFT) substrate and a method for manufacturing the same are provided. The method includes: sequentially forming a plurality of light-shielding portions, a buffer layer, and a plurality of island-shaped polysilicon portions on a substrate; performing light ion doping over two sides of the island-shaped polysilicon portions to form doped regions and channel regions; sequentially forming a gate insulating layer and a plurality of gate electrodes; performing heavy ion doping over the doped region that are not covered by the gate electrodes to form N-type heavily doped regions and N-type lightly doped regions; and forming an interlayer insulating layer as well as a source electrode and a drain electrode which are electrically connected to the N-type heavily doped regions on the gate electrodes.

公开(公告)号：US20180083047A1

公开(公告)日：2018-03-22

申请号：US15039853

申请日：2016-05-13

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Tao Wang

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/027 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/308 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/1222 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/1218 ,  H01L27/1248 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/78675 ,  H01L29/78696

Abstract: The present invention provides a TFT substrate and a manufacture method thereof. The TFT substrate involves modifications made on the structure of an active layer (410) of a TFT (400) to form at least one step on each of two side portions of the active layer (410). Compared to an active layer of the prior art, electric field concentration effect at acute points on two side surfaces of the active layer (410) can be effectively reduced, making charge carrier concentration in the interior of the active layer (410) uniform and electrical property of output of the TFT (400) stable, whereby the quality of the TFT (400) is made high and the operation stability of the TFT substrate is enhanced. The manufacture method of a TFT substrate according to the present invention effectively reduces electric field concentration effect at acute points on side surfaces of an active layer (410) of a TFT (400), making charge carrier concentration in the interior of the active layer (410) uniform and electrical property of output of the TFT (400) stable, whereby the quality of the TFT (400) is made high and the operation stability of the TFT substrate is enhanced.