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公开(公告)号：US10394574B2
公开(公告)日：2019-08-27
申请号：US15171388
申请日：2016-06-02
Applicant: VIA Alliance Semiconductor Co., Ltd.
Inventor： Fengxia Wu , Tian Shen , Zhou Hong , Yuanfeng Wang
Abstract: An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct the MXU to allocate space of the ring buffer for a first hardware thread and subsequently write second commands of the first hardware thread into the allocated space of the ring buffer according to an instruction of a kernel.
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公开(公告)号：US10250896B2
公开(公告)日：2019-04-02
申请号：US15287857
申请日：2016-10-07
Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
Inventor： Heng Que , Deming Gu , Zhou Hong , Yuanfeng Wang
IPC: H04N19/176 , H04N19/17 , H04N19/436 , H04N19/593
Abstract: An image compression method based on JPEG-LS is presented. In the method, the M×N pixels in the source image are divided into k groups. M, N, and k are all integers larger than one. Each group corresponds to a plurality of pixels among the M×N pixels. The decorrelation procedure and the context modeling procedure are performed for each of the plurality of pixels in the ith group of the k groups. The compensation look-up table is not refreshed until all pixels in the ith group are performed with the decorrelation procedure and the context modeling procedure.
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公开(公告)号：US10037590B2
公开(公告)日：2018-07-31
申请号：US14836102
申请日：2015-08-26
Applicant: VIA Alliance Semiconductor Co., Ltd.
Inventor： Fengxia Wu , Yuanfeng Wang , Zhou Hong , Heng Que
CPC classification number: G06T1/20 , G06F1/3287 , G06T1/60 , G06T7/50 , G06T11/001 , G06T11/20 , G06T11/60 , G09G5/10 , G09G2330/021 , Y02D10/171
Abstract: A graphics processing unit and associated graphics processing method are provided. The graphics processing unit includes: an execution unit, for performing shader execution and texture loading; a fixed-function unit, for executing a graphics rendering pipeline; a memory-access unit; a texture unit, for reading texture data from a memory via the memory-access unit according to the data requirement of the execution unit or the fixed-function unit; and a command stream parser, for receiving a draw command from a display driver, and transmitting the draw command to the execution unit or the fixed-function unit to perform graphics processing according to the type of draw command. When the command stream parser determines that the draw command is a specific draw command, the command stream parser transmits the draw command only to the fixed-function unit to perform graphics processing, and turns off power to the execution unit.
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公开(公告)号：US09959660B2
公开(公告)日：2018-05-01
申请号：US15174253
申请日：2016-06-06
Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
Inventor： Fengxia Wu , Wei Zhang , Zhou Hong , Yuanfeng Wang
CPC classification number: G06T15/005 , G06T1/60 , G06T15/80 , G06T19/20 , G06T2200/04 , G06T2200/28
Abstract: A device for image processing includes a first queue, a second queue, a cache, and a processor. The first queue is capable of receiving a first image tile. The processor is electrically connected to the first queue, the second queue, and the cache, respectively. The processor is capable of obtaining the first image tile from the first queue and obtaining mask information of the background mask corresponding to the first tile from the cache. The processor determines the relationship between the first image tile and the background mask based on the first image tile and the mask information so as to selectively transfer the first image tile to the second queue.
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公开(公告)号：US09804659B2
公开(公告)日：2017-10-31
申请号：US14930944
申请日：2015-11-03
Applicant: VIA Alliance Semiconductor Co., Ltd.
CPC classification number: G06F1/324 , G06F1/32 , G06F1/3275 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/067 , G06F15/78 , Y02D10/12 , Y02D10/13
Abstract: An on-chip sensor hub fabricated on a chip with a main processor of a mobile device, and the mobile device, and a method for multi-sensor management on the mobile device. An on-chip sensor hub includes a co-processor and uses an inter-process communication interface. The co-processor and main processor of the mobile device are fabricated on the same chip and communicate with each other via the inter-process communication interface. The co-processor controls a plurality of sensors in the mobile device in accordance with requests issued from the main processor. The co-processor further collects and manages sensor data from the sensors to be processed by the main processor.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09892541B2
公开(公告)日：2018-02-13
申请号：US14919799
申请日：2015-10-22
Applicant: VIA Alliance Semiconductor Co., Ltd.
Inventor： Huaisheng Zhang , Zhou Hong , Xiaowei Yao
CPC classification number: G06T15/005 , G06T1/20
Abstract: A method for a programmable primitive setup in a 3D graphics pipeline is introduced to contain at least the following steps. Information about first and third primitives is obtained from a buffer. The information about all or a portion of the first primitives is packed and sent to an SS (Setup Shader) thread. Information about a second primitive to be clipped is packed and sent to a GBS (Guard-Band-clipping Shader) thread. The information about all or a portion of the third primitives is packed and sent to an AS (Attribute Shader) thread.
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公开(公告)号：US10606335B2
公开(公告)日：2020-03-31
申请号：US15510266
申请日：2014-12-12
Applicant: VIA Alliance Semiconductor Co., Ltd.
IPC: G06F1/32 , G06F1/324 , G06F1/3296
Abstract: A dynamic voltage frequency scaling (DVFS) system is provided. The DVFS system includes: a computation unit, a power management unit (PMU), a hardware activity monitor (HAM), and a hardware voltage monitor (HVM). The HAM monitors a working status and temperature information of the computation unit, and determines whether to update an operating voltage and frequency of the computation unit according to the working status, the temperature information, and a previous determination result. When the HAM determines to update the operating voltage and frequency, the HAM generates a first control signal to the PMU to calibrate the operating voltage and frequency. The HVM detects timing information of the computation unit and determine whether to fine-tune the operating voltage according to the detected timing information. When the HVM determines to fine-tune the operating voltage, the hardware monitor generates a second control signal to the PMU to fine-tune the operating voltage.
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公开(公告)号：US10304212B2
公开(公告)日：2019-05-28
申请号：US15299481
申请日：2016-10-21
Applicant: VIA Alliance Semiconductor Co., Ltd.
Abstract: A graphic data compression device includes a processing unit for processing graphic data and a mixed-type compression unit for compressing the data processed by the processing unit. The mixed-type compression unit includes a lossless compression module and a nearly-lossless compression module. The lossless compression module performs a compression on processed data by a lossless compression algorithm. The nearly-lossless compression module includes an adjustment module and a compression module. The adjustment module performs an adjustment on the processed data to reduce a size of the processed data. The compression module performs, by the lossless compression algorithm, a compression on the data adjusted by the adjustment module. A graphic data compression method of the graphic data compression device is also provided. The graphic data compression device and method of the present invention reduce bandwidth load and memory occupancy, thereby effectively improving the usage of memory capacity.
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9.发明授权公开(公告)号：US10007557B2
公开(公告)日：2018-06-26
申请号：US15171420
申请日：2016-06-02
Applicant: VIA Alliance Semiconductor Co., Ltd.
IPC: G06F13/14 , G06F9/50 , G06F13/366 , G06F11/30 , G06F13/40
CPC classification number: G06F9/5011 , G06F9/52 , G06F11/3024 , G06F11/3041 , G06F11/3433 , G06F13/366 , G06F13/4031
Abstract: A computing resource controller controlling how multiple engines share a shared resource. The controller has an arbiter, a monitoring module, an arbiter strategy control center, and an arbiter parameter updating module. The arbiter allocates access rights to the shared resource to the engines. The monitor module monitors the demands for the shared resource requested by the engines. Based on monitored results obtained from the monitoring module, the arbiter strategy control center determines an arbiter strategy suitable to the arbiter and, accordingly, the arbiter parameter updating module sets parameters of the arbiter, and the arbiter uses newly-set parameters to allocate the access rights to the shared resource to the engines.
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公开(公告)号：US09904550B2
公开(公告)日：2018-02-27
申请号：US14855580
申请日：2015-09-16
Applicant: VIA Alliance Semiconductor Co., Ltd.
Inventor： Huaisheng Zhang , Zhou Hong , Heng Qi
CPC classification number: G06F9/30181 , G06F8/41 , G06F8/447 , G06F8/456 , G06F9/3001 , G06F9/3005 , G06F9/3802 , G06F9/3853
Abstract: A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).
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