公开(公告)号：US20240371695A1

公开(公告)日：2024-11-07

申请号：US18204398

申请日：2023-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo

IPC: H01L21/78 ,  H01L29/06

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.

公开(公告)号：US12040354B2

公开(公告)日：2024-07-16

申请号：US18119009

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chu-Fu Lin ,  Chun-Hung Chen

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/91

Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

公开(公告)号：US20150311117A1

公开(公告)日：2015-10-29

申请号：US14791265

申请日：2015-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/302 ,  H01L21/283

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US08884398B2

公开(公告)日：2014-11-11

申请号：US13854142

申请日：2013-04-01

Applicant: United Microelectronics Corp.

Inventor： Chu-Fu Lin ,  Chien-Li Kuo ,  Ching-Li Yang

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/00

CPC classification number: H01L23/5252 ,  H01L23/525 ,  H01L23/5254 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.

Abstract translation: 反熔丝编程方法包括以下步骤。 首先，提供绝缘层。 在绝缘层上限定反熔丝区域。 反熔丝嵌入在绝缘层的反熔丝区域内。 反熔丝包括至少第一导体和第二导体。 然后，通过激光去除绝缘层的一部分，以在绝缘层中形成抗熔丝开口。 第一导体的一部分和第二导体的一部分通过反熔丝开口露出。 之后，在反熔丝开口中形成凸起下的金属层，以电连接第一导体和第二导体。

公开(公告)号：US12034038B2

公开(公告)日：2024-07-09

申请号：US18119043

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chu-Fu Lin ,  Chun-Hung Chen

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/91

Abstract: A method for manufacturing a capacitor structure is provided. A substrate having a first side and a second side opposite to the first side is provided. A plurality of first trenches are formed on the first side. A first capacitor is formed extending along the first side and into the first trenches. A plurality of second trenches are formed on the second side. A second capacitor is formed extending along the second side and into the second trenches.

公开(公告)号：US20190221528A1

公开(公告)日：2019-07-18

申请号：US16361880

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US20190013259A1

公开(公告)日：2019-01-10

申请号：US15642349

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chun-Hung Chen ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.

公开(公告)号：US09035457B2

公开(公告)日：2015-05-19

申请号：US13689727

申请日：2012-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract translation: 提出了具有集成无源器件的基板及其制造方法。 衬底可以包括通过硅通孔，具有第一无源器件图案和堆叠通孔的至少一个再分布层，以及具有第二无源器件图案的下凸块金属层。

公开(公告)号：US20240315095A1

公开(公告)日：2024-09-19

申请号：US18135741

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Yi-Feng Hsu

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

公开(公告)号：US10886241B1

公开(公告)日：2021-01-05

申请号：US17023967

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.