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公开(公告)号：US10910386B2
公开(公告)日：2021-02-02
申请号：US15943721
申请日：2018-04-03
Inventor： Wei-Lun Hsu , Hung-Lin Shih , Che-Hung Huang , Ping-Cheng Hsu , Hsu-Yang Wang
IPC: H01L27/10 , H01L27/108 , H01L21/768 , H01L21/762 , H01L21/8234 , H01L21/8238
Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.
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公开(公告)号：US20200083228A1
公开(公告)日：2020-03-12
申请号：US16145164
申请日：2018-09-28
Inventor： Shih-Kuei Yen , Li-Wei Liu , Le-Tien Jung , Hung-Lin Shih , Hsuan-Tung Chu , Ming-Che Li , Guan-Yi Liou , Huai-Jin Hsing
IPC: H01L27/108 , H01L27/11519 , H01L27/11551 , H01L27/11526
Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
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公开(公告)号：US20160172190A1
公开(公告)日：2016-06-16
申请号：US14571249
申请日：2014-12-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Lin Shih , Chueh-Yang Liu , Shao-Wei Wang , Che-Hung Huang , Po-Hua Jen , Shih-Hao Su
IPC: H01L21/02 , H01L21/283
CPC classification number: H01L21/28211 , H01L21/76224 , H01L21/823462
Abstract: A gate oxide formation process includes the following steps. A first gate oxide layer is formed on a substrate. The first gate oxide layer is thinned to a first predetermined thickness. The first gate oxide layer is then thickened to a second predetermined thickness, to thereby form a second gate oxide layer.
Abstract translation: 栅极氧化物形成工艺包括以下步骤。 在基板上形成第一栅氧化层。 第一栅极氧化物层被薄化到第一预定厚度。 然后将第一栅极氧化物层增厚至第二预定厚度，从而形成第二栅极氧化物层。
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公开(公告)号：US11665888B2
公开(公告)日：2023-05-30
申请号：US17134193
申请日：2020-12-25
Inventor： Wei-Lun Hsu , Hung-Lin Shih , Che-Hung Huang , Ping-Cheng Hsu , Hsu-Yang Wang
IPC: H01L21/00 , H01L21/768 , H01L21/762 , H01L21/8234 , H01L21/8238
CPC classification number: H10B12/485 , H01L21/76224 , H01L21/76877 , H10B12/053 , H01L21/823481 , H01L21/823878 , H10B12/482
Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.
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公开(公告)号：US11069690B2
公开(公告)日：2021-07-20
申请号：US16145164
申请日：2018-09-28
Inventor： Shih-Kuei Yen , Li-Wei Liu , Le-Tien Jung , Hung-Lin Shih , Hsuan-Tung Chu , Ming-Che Li , Guan-Yi Liou , Huai-Jin Hsing
IPC: H01L27/108 , H01L27/11519 , H01L27/11551 , H01L27/11526
Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
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Patent Agency Ranking
公开(公告)号：US10008599B1
公开(公告)日：2018-06-26
申请号：US15446009
申请日：2017-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Lun Hsu , Hsin-Che Huang , Shyan-Liang Chou , Hung-Lin Shih
IPC: H01L29/78 , H01L27/092 , H01L29/06 , H01L21/8238 , H01L21/762 , H01L21/02
CPC classification number: H01L29/7846 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L27/092 , H01L27/0924 , H01L29/0649
Abstract: A complementary metal oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate with a first device region and a second device region formed thereon. A first isolation structure is formed in the first device region, and includes a first trench filled with a first material. A second isolation structure is formed in the second device region and includes a second trench filled with a second material. The first material and the second material have different stresses. A first gate structure is disposed atop the first material and completely covering the first trench. A second gate structure is disposed atop the second material and completely covering the second trench.
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公开(公告)号：US08951884B1
公开(公告)日：2015-02-10
申请号：US14079648
申请日：2013-11-14
Applicant: United Microelectronics Corp.
Inventor： Hung-Lin Shih , Jei-Ming Chen , Chih-Chien Liu , Chin-Fu Lin , Kuan-Hsien Li
IPC: H01L21/76 , H01L29/423 , H01L21/8234 , H01L21/02 , H01L21/306
CPC classification number: H01L21/30604 , H01L21/823431 , H01L21/823462 , H01L29/401
Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
Abstract translation: 一种用于形成FinFET结构的方法包括提供衬底，第一区和限定在衬底上的第二区，分别在第一区和第二区内的衬底上设置第一鳍结构和第二鳍结构。 第一氧化物层覆盖第一鳍结构和第二鳍结构。 接下来，依次在基板和第一氧化物层上完全形成第一保护层和第二保护层，去除第一区域内的第二保护层，然后去除第一区域内的第一保护层。 之后，同时除去覆盖第二区域内的第一鳍结构和第二保护层的第一氧化物层，形成第二氧化物层以覆盖第一鳍结构。
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公开(公告)号：US20210118889A1
公开(公告)日：2021-04-22
申请号：US17134193
申请日：2020-12-25
Inventor： Wei-Lun Hsu , Hung-Lin Shih , Che-Hung Huang , Ping-Cheng Hsu , Hsu-Yang Wang
IPC: H01L27/108 , H01L21/768 , H01L21/762
Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.
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公开(公告)号：US10475925B2
公开(公告)日：2019-11-12
申请号：US15985683
申请日：2018-05-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Lun Hsu , Hsin-Che Huang , Shyan-Liang Chou , Hung-Lin Shih
IPC: H01L21/762 , H01L29/78 , H01L27/092 , H01L29/06 , H01L21/8238
Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.
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公开(公告)号：US20190279989A1
公开(公告)日：2019-09-12
申请号：US15943721
申请日：2018-04-03
Inventor： Wei-Lun Hsu , Hung-Lin Shih , Che-Hung Huang , Ping-Cheng Hsu , Hsu-Yang Wang
IPC: H01L27/108 , H01L21/762 , H01L21/768
Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.
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