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公开(公告)号：US20220216345A1
公开(公告)日：2022-07-07
申请号：US17705380
申请日：2022-03-27
Applicant: United Microelectronics Corp.
Inventor： Su Xing , Chung Yi Chiu , Hai Biao Yao
IPC: H01L29/786 , H01L29/66 , H01L29/06 , H01L21/8232 , H01L21/225 , H01L21/762 , H01L29/749
Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.
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公开(公告)号：US11448318B2
公开(公告)日：2022-09-20
申请号：US16889816
申请日：2020-06-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hai Biao Yao , Su Xing , Jinyu Liao , Purakh Raj Verma
Abstract: The invention provides a seal ring structure, which comprises a substrate, and a seal ring positioned on the substrate, wherein the seal ring comprises an inner seal ring comprising a plurality of inner seal units, wherein each of the inner seal units is arranged at intervals with each other, an outer seal ring comprising a plurality of outer seal units arranged at the periphery of the inner seal ring, wherein each of the outer seal units is arranged at intervals with each other, and a plurality of groups of fence-shaped seal units, wherein at least one group of fence-shaped seal units is positioned between one of the inner seal units and the other adjacent outer seal unit.
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公开(公告)号：US11462618B2
公开(公告)日：2022-10-04
申请号：US17191720
申请日：2021-03-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hai Biao Yao , Su Xing
IPC: H01L29/10 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/36 , H01L29/66 , H01L21/266 , H01L21/265 , H01L29/167
Abstract: An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region. The embedded doping region acts as a hole sink to alleviate or avoid floating body effects.
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Patent Agency Ranking
公开(公告)号：US11329161B2
公开(公告)日：2022-05-10
申请号：US16907001
申请日：2020-06-19
Applicant: United Microelectronics Corp.
Inventor： Su Xing , Chung Yi Chiu , Hai Biao Yao
IPC: H01L29/786 , H01L29/06 , H01L21/762 , H01L29/66 , H01L21/8232 , H01L21/225 , H01L29/749
Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.
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公开(公告)号：US20210351302A1
公开(公告)日：2021-11-11
申请号：US16907001
申请日：2020-06-19
Applicant: United Microelectronics Corp.
Inventor： Su Xing , Chung Yi Chiu , Hai Biao Yao
IPC: H01L29/786 , H01L29/06 , H01L29/66
Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.
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公开(公告)号：US11804550B2
公开(公告)日：2023-10-31
申请号：US17705376
申请日：2022-03-27
Applicant: United Microelectronics Corp.
Inventor： Su Xing , Chung Yi Chiu , Hai Biao Yao
IPC: H01L29/06 , H01L21/8232 , H01L21/225 , H01L21/762 , H01L29/749 , H01L29/786 , H01L29/66
CPC classification number: H01L29/78603 , H01L21/2253 , H01L21/762 , H01L21/8232 , H01L29/0653 , H01L29/66772 , H01L29/749
Abstract: A method for fabricating a field-effect transistor includes the following steps. A gate structure layer in a line shape including a first region and a second region abutting to the first region is formed on a silicon layer. A first implanting process is performed to implant first-type dopants at least into a second portion of the second region of the gate structure layer. A second implanting region is performed to implant second-type dopants into the silicon layer to form a source region and a second region corresponding to the first region of the gate structure layer. The gate structure layer has a conductive-type junction at an interface between the first and second portions of the second region. A width of the silicon layer under the second region of the gate structure layer is smaller than a width of the gate structure layer.
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公开(公告)号：US11799031B2
公开(公告)日：2023-10-24
申请号：US17705380
申请日：2022-03-27
Applicant: United Microelectronics Corp.
Inventor： Su Xing , Chung Yi Chiu , Hai Biao Yao
IPC: H01L21/8232 , H01L21/762 , H01L29/749 , H01L29/786 , H01L29/66 , H01L29/06 , H01L21/225
CPC classification number: H01L29/78603 , H01L21/2253 , H01L21/762 , H01L21/8232 , H01L29/0653 , H01L29/66772 , H01L29/749
Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.
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公开(公告)号：US20220216344A1
公开(公告)日：2022-07-07
申请号：US17705376
申请日：2022-03-27
Applicant: United Microelectronics Corp.
Inventor： Su Xing , Chung Yi Chiu , Hai Biao Yao
IPC: H01L29/786 , H01L29/66 , H01L29/06 , H01L21/8232 , H01L21/225 , H01L21/762 , H01L29/749
Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.
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