公开(公告)号：US06674173B1

公开(公告)日：2004-01-06

申请号：US10336497

申请日：2003-01-02

Applicant: Tsing-Chow Wang

Inventor： Tsing-Chow Wang

IPC: H01L23495

CPC classification number: H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/1433 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor die package design incorporating at least a pair of functional semiconductor dies. The input/output pads locations on one of the dies (the daughter die) are located at the near mirror image of the original die (mother die). The package architecture includes two dies back-to-back or stacked dies back-to-back, therefore a plurality of input/output interconnections can be formed. The package increases density and performance by twofold or more compared to a regular package containing only one die with the same footprint. At least one additional pin can be dedicated as the chip select pin for the daughter die or multiple dies. The other pins can be shared with the mother die.

Abstract translation: 包括至少一对功能半导体管芯的半导体管芯封装设计。 一个管芯（子管芯）上的输入/输出焊盘位置位于原始管芯（母模）的近镜面处。 封装结构包括背对背或背对背叠层的两个管芯，因此可以形成多个输入/输出互连。 与仅具有相同占地面积的一个模具的普通包装相比，封装将密度和性能提高了两倍或更多。 至少一个额外的引脚可以作为子芯片或多个芯片的芯片选择引脚。 其他引脚可以与母模共用。

公开(公告)号：US4501975A

公开(公告)日：1985-02-26

申请号：US349414

申请日：1982-02-16

Applicant: Richard M. Josephs ,  Tsing-Chow Wang

Inventor： Richard M. Josephs ,  Tsing-Chow Wang

IPC: H03K3/037 ,  H03K3/38 ,  H03K19/195 ,  H03K3/00

CPC classification number: H03K3/38 ,  H03K19/1954 ,  Y10S505/864

Abstract: A Josephson junction latch circuit is provided which has an AND gate having plural inputs and a single output. The output of the single AND gate is directly coupled to a Josephson junction flux storage loop capable of storing flux indicative of the output of the AND gate. A Josephson junction sense line is provided capable of sensing the flux condition of the flux storage loop. The sense line is directly coupled to amplifying gates which produce amplified true and complement quantities whenever the sense line is actuated.

Abstract translation: 提供了具有多个输入和单个输出的与门的约瑟夫逊结锁存电路。 单个AND门的输出直接耦合到能够存储指示与门输出的通量的约瑟夫逊结通量存储回路。 提供约瑟夫逊结感测线，其能够感测磁通量存储回路的通量条件。 感测线直接耦合到放大门，每当感测线被驱动时，其产生放大的真实和补充量。

公开(公告)号：US4413197A

公开(公告)日：1983-11-01

申请号：US298149

申请日：1981-08-31

Applicant: Richard M. Josephs ,  Tsing-Chow Wang

Inventor： Richard M. Josephs ,  Tsing-Chow Wang

IPC: H03K19/195

CPC classification number: H03K19/1954 ,  Y10S505/859

Abstract: A Josephson junction AND gate logic circuit is provided which has an enhanced and improved operating window area. The circuit comprises two parallel branches one for the input and one for the output connected between a biasing current source and a ground or reference voltage. The input branch is provided with a first branch resistor, a third Josephson junction and an interferometer in series between the current source and ground. A plurality of input gate signal lines connects to the interferometer and a sink resistor is connected in parallel with the interferometer. When the input current signals collectively exceed a predetermined level, the two Josephson junctions in the interferometer switch ON and assume the high impedance state. The input current and biasing current is diverted into the output branch causing the second Josephson junction in the output branch to switch ON. The biasing current in the output branch creates a high-gain current to the load circuit connected in parallel with the second Josephson junction.

Abstract translation: 提供了约瑟夫逊结AND门逻辑电路，其具有增强和改进的操作窗口区域。 该电路包括两个平行分支，一个用于输入，一个用于连接在偏置电流源和接地或参考电压之间的输出。 输入支路设置有电流源和地之间的第一分支电阻器，第三约瑟夫逊结和干涉仪。 多个输入栅极信号线连接到干涉仪，并且吸收电阻器与干涉仪并联连接。 当输入电流信号共同超过预定电平时，干涉仪中的两个约瑟夫逊结接通并呈现高阻态。 输入电流和偏置电流被转移到输出分支中，导致输出分支中的第二约瑟夫逊结接通。 输出支路中的偏置电流产生与第二个约瑟夫逊结并联连接的负载电路的高增益电流。

公开(公告)号：US08721194B2

公开(公告)日：2014-05-13

申请号：US13613598

申请日：2012-09-13

Applicant: Yun-Cheng Huang ,  Chi-Min Ting ,  Tsing-Chow Wang ,  Chung Hsin Fu

Inventor： Yun-Cheng Huang ,  Chi-Min Ting ,  Tsing-Chow Wang ,  Chung Hsin Fu

IPC: G02B6/36 ,  G02B6/26 ,  G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4214 ,  G02B6/264 ,  G02B6/4201 ,  G02B6/4204 ,  G02B6/4246 ,  G02B6/4249 ,  G02B6/425 ,  G02B6/4256 ,  G02B6/426 ,  G02B6/4292 ,  G02B6/43

Abstract: The present invention provides an optical transceiver module, comprising: a circuit substrate; a z-axis positioning base connected to the circuit substrate that, wherein the z-axis positioning base comprises two first sides respectively provided on two lateral sides of the optical transceiver sub-module, a second side provided between and connecting the two first sides, an opening corresponding in position to a side of the optical transceiver sub-module that faces away from the second side, and a step difference provided on each of the two first sides and the second side; a fiber-optic lens element provided on the z-axis positioning base and comprises a cover and a fiber-optic lens sub-module, wherein the cover comprises a recess and step differences surrounding the recess and respectively corresponding in position to the step differences provided on the z-axis positioning base, so as for the cover to be fitted on the z-axis positioning base.

Abstract translation: 本发明提供了一种光收发器模块，包括：电路基板; 连接到所述电路基板的z轴定位基座，其中所述z轴定位基座包括分别设置在所述光收发器子模块的两个侧面上的两个第一侧，设置在所述两个第一侧之间并连接所述两个第一侧的第二侧， 位于所述光收发器子模块的背离所述第二侧的位置的开口以及设置在所述两个第一侧和所述第二侧中的每一个上的台阶差; 设置在所述z轴定位基座上并且包括盖和光纤透镜子模块的光纤透镜元件，其中所述盖包括凹部和围绕所述凹部的台阶差，并且分别对应于所提供的台阶差的位置 在z轴定位底座上，以便将盖安装在z轴定位座上。

公开(公告)号：US20080128476A1

公开(公告)日：2008-06-05

申请号：US11859163

申请日：2007-09-21

Applicant: Tsing-Chow Wang ,  Runling Li

Inventor： Tsing-Chow Wang ,  Runling Li

IPC: B23K31/02

CPC classification number: B23K3/0623 ,  H01L24/11 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/1181 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A fluxless reflow process for bump formation is provided, which includes: a purifying process for keeping solder in a state of melting or half-melting for 40 s to 540 s; a ball-forming process for melting the solder completely to form ball-like bumps; and a cooling process. The splashing of solder can be avoided and the defect that there may be solder balls around the bumps can be eliminated.

Abstract translation: 提供了一种用于凸块形成的无助焊剂回流工艺，其包括：将焊料保持在熔化或半熔化状态40秒至540秒的净化方法; 用于完全熔化焊料以形成球状凸起的滚珠成形工艺; 和冷却过程。 可以避免溅射溅射，并且可以消除在凸块周围可能存在焊球的缺陷。

公开(公告)号：US06316831B1

公开(公告)日：2001-11-13

申请号：US09564589

申请日：2000-05-05

Applicant: Tsing-Chow Wang

Inventor： Tsing-Chow Wang

IPC: H01L2348

CPC classification number: H01L24/12 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: Within both a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing, the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is then formed over the patterned bond pad layer a barrier layer comprising: (1) a first titanium-tungsten alloy layer; (2) a titanium-tungsten alloy nitride layer formed upon the first titanium-tungsten alloy layer; and (3) a second titanium-tungsten alloy layer formed upon the titanium-tungsten alloy nitride layer. Finally, there is then formed upon the barrier layer a seed layer which comprises a titanium layer formed upon the barrier layer. The method contemplates a microelectronic fabrication fabricated employing the method. The barrier layer provides enhanced barrier properties within the microelectronic fabrication within which is formed the barrier layer.

Abstract translation: 在制造微电子制造的方法和使用的微电子制造两者中，首先提供了一种基板。 在该方法中，然后在衬底上形成图案化的接合焊盘层。 然后在图案化的接合焊盘层上形成阻挡层，该阻挡层包括：（1）第一钛 - 钨合金层; （2）形成在第一钛 - 钨合金层上的钛 - 钨合金氮化物层; 和（3）形成在钛 - 钨合金氮化物层上的第二钛 - 钨合金层。 最后，在阻挡层上形成包含形成在阻挡层上的钛层的晶种层。 该方法考虑使用该方法制造的微电子制造。 阻挡层在微电子制造中提供增强的阻挡性能，其中形成阻挡层。

公开(公告)号：US20130287406A1

公开(公告)日：2013-10-31

申请号：US13613598

申请日：2012-09-13

Applicant: Yun-Cheng HUANG ,  Chi-Min Ting ,  Tsing-Chow Wang ,  Chung Hsin Fu

Inventor： Yun-Cheng HUANG ,  Chi-Min Ting ,  Tsing-Chow Wang ,  Chung Hsin Fu

IPC: H04B10/14

CPC classification number: G02B6/4214 ,  G02B6/264 ,  G02B6/4201 ,  G02B6/4204 ,  G02B6/4246 ,  G02B6/4249 ,  G02B6/425 ,  G02B6/4256 ,  G02B6/426 ,  G02B6/4292 ,  G02B6/43

Abstract: The present invention provides an optical transceiver module, comprising: a circuit substrate; a z-axis positioning base connected to the circuit substrate that, wherein the z-axis positioning base comprises two first sides respectively provided on two lateral sides of the optical transceiver sub-module, a second side provided between and connecting the two first sides, an opening corresponding in position to a side of the optical transceiver sub-module that faces away from the second side, and a step difference provided on each of the two first sides and the second side; a fiber-optic lens element provided on the z-axis positioning base and comprises a cover and a fiber-optic lens sub-module, wherein the cover comprises a recess and step differences surrounding the recess and respectively corresponding in position to the step differences provided on the z-axis positioning base, so as for the cover to be fitted on the z-axis positioning base.

Abstract translation: 本发明提供了一种光收发器模块，包括：电路基板; 连接到所述电路基板的z轴定位基座，其中所述z轴定位基座包括分别设置在所述光收发器子模块的两个侧面上的两个第一侧，设置在所述两个第一侧之间并连接所述两个第一侧的第二侧， 位于所述光收发器子模块的背离所述第二侧的位置的开口以及设置在所述两个第一侧和所述第二侧中的每一个上的台阶差; 设置在所述z轴定位基座上并且包括盖和光纤透镜子模块的光纤透镜元件，其中所述盖包括凹部和围绕所述凹部的台阶差，并且分别对应于所提供的台阶差的位置 在z轴定位底座上，以便将盖安装在z轴定位座上。

公开(公告)号：US06544878B2

公开(公告)日：2003-04-08

申请号：US09970231

申请日：2001-10-03

Applicant: Tsing-Chow Wang

Inventor： Tsing-Chow Wang

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: Within both a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is then formed over the patterned bond pad layer a barrier layer comprising: (1) a first titanium-tungsten alloy layer; (2) a titanium-tungsten alloy nitride layer formed upon the first titanium-tungsten alloy layer; and (3) a second titanium-tungsten alloy layer formed upon the titanium-tungsten alloy nitride layer. Finally, there is then formed upon the barrier layer a seed layer which comprises a titanium layer formed upon the barrier layer. The method contemplates a microelectronic fabrication fabricated employing the method. The barrier layer provides enhanced barrier properties within the microelectronic fabrication within which is formed the barrier layer.

Abstract translation: 在制造微电子制造的方法和使用该方法制造的微电子制造两者中，首先提供了一种衬底。 在该方法中，然后在衬底上形成图案化的接合焊盘层。 然后在图案化的接合焊盘层上形成阻挡层，该阻挡层包括：（1）第一钛 - 钨合金层; （2）形成在第一钛 - 钨合金层上的钛 - 钨合金氮化物层; 和（3）形成在钛 - 钨合金氮化物层上的第二钛 - 钨合金层。 最后，在阻挡层上形成包含形成在阻挡层上的钛层的晶种层。 该方法考虑使用该方法制造的微电子制造。 阻挡层在微电子制造中提供增强的阻挡性能，其中形成阻挡层。

公开(公告)号：US06281041B1

公开(公告)日：2001-08-28

申请号：US09450545

申请日：1999-11-30

Applicant: Chung W Ho ,  Tsing-Chow Wang

Inventor： Chung W Ho ,  Tsing-Chow Wang

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/13671 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/1025 ,  H05K2201/2081 ,  H05K2203/0315 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Within a method for forming a solder interconnection structure for use within a microelectronic fabrication, there is first provided a substrate having formed thereover a bond pad. There is then formed upon the bond pad a first solder interconnection layer. There is then formed over the first solder interconnection layer an annular solder non-wettable copper oxide layer which does not cover an upper dome portion of the first solder interconnection layer. There is then formed over the upper dome portion of the first solder interconnection layer and not upon the annular solder non-wettable copper oxide layer a second solder interconnection layer.

Abstract translation: 在用于形成在微电子制造中使用的焊料互连结构的方法中，首先提供了在接合焊盘之上形成的衬底。 然后在接合焊盘上形成第一焊料互连层。 然后在第一焊料互连层上形成不覆盖第一焊料互连层的上部圆顶部分的环形焊料不可湿性氧化铜层。 然后形成在第一焊料互连层的上部圆顶部分上，而不是在环形焊料不可湿性氧化铜层上形成第二焊料互连层。

公开(公告)号：US4509146A

公开(公告)日：1985-04-02

申请号：US446129

申请日：1982-12-02

Applicant: Tsing-Chow Wang ,  Richard M. Josephs

Inventor： Tsing-Chow Wang ,  Richard M. Josephs

IPC: G11C11/44 ,  H01L39/22

CPC classification number: G11C11/44 ,  H01L39/223 ,  Y10S505/832

Abstract: A superconductive Josephson junction high density memory array is provided. Each memory cell in the array comprises a two branch superconducting interferometer storage loop which has only a single Josephson junction device in one of the branches. The Josephson junction devices are mounted on a substrate having a patterned ground plane. The ground plane pattern is provided with holes or apertures which surround the Josephson junction devices so that the control current of the control lines couple with the tunnel junctions of the Josephson junction devices but not with the ground plane. This structural arrangement provides a threshold characteristic for the single Josephson junction device which is symmetrical to the gate current, thus, may be easily switched to two current states indicative of two logic states.

Abstract translation: 提供超导约瑟夫逊结高密度存储器阵列。 该阵列中的每个存储单元包括两个分支超导干涉仪存储回路，其中一个分支中仅有一个约瑟夫逊结器件。 约瑟夫逊结装置安装在具有图案化接地平面的基板上。 接地平面图案设置有围绕约瑟夫逊结装置的孔或孔，使得控制线的控制电流与约瑟夫逊结装置的隧道结相耦合，但不与接地平面耦合。 该结构布置为与栅极电流对称的单个约瑟夫森结器件提供阈值特性，因此可以容易地切换到指示两个逻辑状态的两个电流状态。