公开(公告)号：US20190245544A1

公开(公告)日：2019-08-08

申请号：US16047883

申请日：2018-07-27

Applicant: QUENTIN P. HERR

Inventor： QUENTIN P. HERR

IPC: H03K19/195 ,  G06N10/00

CPC classification number: H03K19/1954 ,  G06N10/00 ,  H03K19/1952

Abstract: A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.

公开(公告)号：US07816940B1

公开(公告)日：2010-10-19

申请号：US12535434

申请日：2009-08-04

Applicant: Deepnarayan Gupta ,  Amol Inamdar

Inventor： Deepnarayan Gupta ,  Amol Inamdar

IPC: H03K19/195

CPC classification number: H03K19/01 ,  H03F19/00 ,  H03K11/00 ,  H03K17/92 ,  H03K19/1954

Abstract: Supercooled electronics often use Rapid Single Flux Quantum (RSFQ) digital circuits. The output voltages from RSFQ devices are too low to be directly interfaced with semiconductor electronics, even if the semiconductor electronics are cooled. Techniques for directly interfacing RSFQ digital circuits with semiconductor electronics are disclosed using a novel inverting transimpedance digital amplifier in conjunction with a non-inverting transimpedance digital amplifier to create a differential transimpedance digital amplifier that permits direct interfacing between RSFQ and semiconductor electronics.

Abstract translation: 过冷电子设备通常使用快速单通量（RSFQ）数字电路。 RSFQ器件的输出电压太低，即使半导体电子器件被冷却，也不能与半导体电子器件直接接口。 使用新颖的反相跨阻抗数字放大器结合非反相跨阻抗数字放大器公开了将RSFQ数字电路与半导体电子器件直接接口的技术，以产生允许RSFQ和半导体电子器件之间直接接口的差分跨阻抗数字放大器。

公开(公告)号：US06188236B1

公开(公告)日：2001-02-13

申请号：US08994442

申请日：1997-12-19

Applicant: Erland Wikborg

Inventor： Erland Wikborg

IPC: H03K1995

CPC classification number: H03K19/1954

Abstract: A logic circuit arrangement includes signal input and signal output devices and a number of SFQ circuits having Josephson junctions in which carrier devices are used for carrying digital information. The SFQ circuits are sampled at the input/output for producing DC voltages and a train having at least two single flux quanta is used as a carrier device for information and phase locking between at least two Josephson junctions is used to provide at least two different dynamic states of which at least one provides an output signal.

Abstract translation: 逻辑电路装置包括信号输入和信号输出装置以及具有约瑟夫逊结的多个SFQ电路，其中载波装置用于承载数字信息。 SFQ电路在输入/输出端进行采样以产生直流电压，并且具有至少两个单通量量子的列车被用作用于信息的载体装置，并且使用至少两个约瑟夫逊结之间的相位锁定来提供至少两个不同的动态 其状态至少一个提供输出信号。

公开(公告)号：US5818373A

公开(公告)日：1998-10-06

申请号：US772017

申请日：1996-12-19

Applicant: Vasili Semenov ,  David F. Schneider ,  Jao-Ching Lin ,  Stanislav Polonsky

Inventor： Vasili Semenov ,  David F. Schneider ,  Jao-Ching Lin ,  Stanislav Polonsky

IPC: H03K19/0175 ,  H03K19/195 ,  H03M1/00

CPC classification number: H03K19/0175 ,  H03K19/1954

Abstract: Disclosed herein are circuits and methods for receiving SFQ data pulses from a superconductor signal source, and first and second clock pulses that are substantially equal in frequency but opposite in phase from clock signal sources, and for encoding and converting the SFQ data pulses into a phase-shift-keying coded dc output voltage. The circuit includes RSFQ T-RS flip-flop means, including quantizing means for storing a current in one of two stable states, which is responsive to the first and second clock pulses and the data pulse, for PSK coding the SFQ data pulses. The circuit also includes a SFQ/DC converter, which is coupled to the quantizing means of the RSFQ T-RS flip-flop means and is responsive to a state of the current stored in the quantizing inductance loop, for converting the PSK coded SFQ data pulses into a PSK coded dc voltage.

Abstract translation: 这里公开了用于从超导体信号源接收SFQ数据脉冲的电路和方法，以及在时钟信号源上基本相同但与时钟信号源相反的第一和第二时钟脉冲，以及用于将SFQ数据脉冲编码和转换成相位 交钥匙编码直流输出电压。 电路包括RSFQ T-RS触发器装置，包括用于存储响应于第一和第二时钟脉冲和数据脉冲的两个稳定状态之一的电流的量化装置，用于对SFQ数据脉冲进行PSK编码。 电路还包括SFQ / DC转换器，其耦合到RSFQ T-RS触发器装置的量化装置，并且响应于存储在量化电感环路中的电流的状态，用于转换PSK编码的SFQ数据 脉冲成PSK编码的直流电压。

公开(公告)号：US5598105A

公开(公告)日：1997-01-28

申请号：US562746

申请日：1995-11-27

Applicant: Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

Inventor： Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

IPC: H01L39/22 ,  H03K19/195

CPC classification number: H03K19/1954

Abstract: An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical "1". When the other input pulse arrives while logical "1" is recorded in the first arrival pulse memory section, the AND circuit section produces an AND output which is defined as the AND output of the elementary cell. When a reset signal pulse is applied to a reset terminal, the first arrival pulse memory section is reset.

Abstract translation: 基本单元使用单通量量子作为二值逻辑传播信号，对于构造异步超导逻辑电路是有效的。 基本单元包括一个OR电路部分和一个AND电路部分。 施加到基本单元的两个输入端子的输入脉冲在基本单元中的信号分离部分处被分离，并且被施加到“或”电路部分的两个输入端和“与”电路部分的两个输入端。 OR电路部分的输出被定义为基本单元的OR输出。 在AND电路部分中设置第一到达脉冲存储器部分，并且当输入到AND电路部分的两个输入端子的两个输入脉冲之一到达另一个时，该事实被记录在第一到达脉冲存储器部分中作为逻辑“ 1“。 当在第一到达脉冲存储器部分中记录逻辑“1”时另一个输入脉冲到达时，与电路部分产生被定义为基本单元的与输出的“与”输出。 当将复位信号脉冲施加到复位端子时，第一到达脉冲存储器部分被复位。

公开(公告)号：US5170080A

公开(公告)日：1992-12-08

申请号：US744754

申请日：1991-08-14

Applicant: John H. Murphy ,  Michael R. Daniel ,  John X. Przybysz

Inventor： John H. Murphy ,  Michael R. Daniel ,  John X. Przybysz

IPC: H03K19/195

CPC classification number: H03K19/1954 ,  Y10S505/859

Abstract: Superconducting digital logic circuits constructed in accordance with this invention include a circuit branch having first and second Josephson junctions electrically connected in series with each other, with a junction point between the first and second Josephson junctions connected to a neutral point; a positive bias voltage is connected to one end of the circuit branch, and a negative bias voltage is connected to a second end of the circuit branch; a first rail for applying a first input voltage signal, having a first polarity, and for extracting a first output signal is connected to one end of the circuit branch; and a second rail for applying a second input voltage signal, having a second polarity, and for extracting a second output signal is connected to the other end of the circuit branch. This invention encompasses both the above circuit and the method of signal processing performed by such circuits.

Abstract translation: 根据本发明构造的超导数字逻辑电路包括具有彼此串联电连接的第一和第二约瑟夫逊结的电路分支，第一和第二约瑟夫逊结之间的连接点连接到中性点; 正偏置电压连接到电路支路的一端，负偏置电压连接到电路支路的第二端; 用于施加具有第一极性并用于提取第一输出信号的第一输入电压信号的第一轨道连接到电路分支的一端; 并且用于施加具有第二极性并用于提取第二输出信号的第二输入电压信号的第二轨道连接到电路分支的另一端。 本发明涵盖上述电路和由这些电路执行的信号处理方法。

公开(公告)号：US11848676B2

公开(公告)日：2023-12-19

申请号：US17181869

申请日：2021-02-22

Applicant: Synopsys, Inc.

Inventor： Stephen Whiteley

IPC: H03M1/60 ,  H03K3/38 ,  G06N10/00 ,  H03K17/92 ,  H03K19/195 ,  H10N60/12 ,  G01R33/035

CPC classification number: H03K3/38 ,  G06N10/00 ,  H03K17/92 ,  G01R33/035 ,  H03K19/195 ,  H03K19/1954 ,  H10N60/12

Abstract: The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuitry minimizes generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.

公开(公告)号：US09710586B2

公开(公告)日：2017-07-18

申请号：US14412344

申请日：2013-07-02

Applicant: Stellenbosch University

Inventor： Louis Crouse Muller ,  Coenrad Johann Fourie

IPC: G06F17/50 ,  H03K19/195

CPC classification number: G06F17/5059 ,  G06F17/5022 ,  G06F17/5045 ,  H03K19/1954

Abstract: The invention provides a method and system for extracting a state machine representation of a digital logic superconductive circuit from an alphanumeric representation of the circuit. The alphanumeric representation typically specifies circuit components including inductive elements, their interconnectivity and input and output nodes. The method according to the invention comprising the steps of simulating the circuit in a suitable software environment utilizing the alphanumeric representation; identifying inductive loops in the circuit; identifying inductive loops in the circuit capable of storing one or more magnetic fluxons and discarding all others; and extracting the state machine representation, using only the inductive loops in the circuit capable of storing magnetic fluxons.

公开(公告)号：US09692423B2

公开(公告)日：2017-06-27

申请号：US14584659

申请日：2014-12-29

Applicant: Robert Francis McDermott, III ,  Britton Louis Thomas Plourde ,  Maxim George Vavilov ,  Frank Karsten Wilhelm-Mauch ,  Luke Colin Gene Govia ,  Emily Joy Pritchett

Inventor： Robert Francis McDermott, III ,  Britton Louis Thomas Plourde ,  Maxim George Vavilov ,  Frank Karsten Wilhelm-Mauch ,  Luke Colin Gene Govia ,  Emily Joy Pritchett

IPC: H03K19/19 ,  H03K19/195 ,  B82Y10/00 ,  G06N99/00

CPC classification number: H03K19/1954 ,  B82Y10/00 ,  G06N99/002 ,  H03K19/19 ,  H03K19/195 ,  H03K19/1958

Abstract: A system for quantum computation and a readout method using the same are provided. In some aspects, the system includes at least one qubit circuit coupled to a resonant cavity, wherein each of the at least one qubit circuit is described by multiple quantum states, and a controller configured to provide microwave irradiation to the resonant cavity such that a quantum state information of the at least one qubit circuit is transferred to a resonant cavity occupation. The system also includes a readout circuit, coupled to the resonant cavity, configured to receive signals corresponding to the resonant cavity occupation, and generate an output indicative of the quantum states of the at least one qubit circuit. Optionally, the system further includes at least one single flux quantum (“SFQ”) circuit coupled to the readout circuit and configured to receive the output therefrom.

公开(公告)号：US09548742B1

公开(公告)日：2017-01-17

申请号：US14754243

申请日：2015-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Baleegh Abdo

IPC: H01P5/12 ,  H03K19/195 ,  H03K3/38 ,  H01P5/103

CPC classification number: H01L39/025 ,  H01L39/2493 ,  H01P5/103 ,  H01P5/12 ,  H01P5/16 ,  H01P5/19 ,  H01P11/001 ,  H03D7/005 ,  H03F7/00 ,  H03F19/00 ,  H03K3/38 ,  H03K19/1954

Abstract: An on-chip Josephson parametric converter is provided. The on-chip Josephson parametric converter includes a Josephson ring modulator. The on-chip Josephson parametric converter further includes a lossless power divider, coupled to the Josephson ring modulator, having a single input port and two output ports for receiving a pump drive signal via the single input port, splitting the pump drive signal symmetrically into two signals that are equal in amplitude and phase, and outputting each of the two signals from a respective one of the two output ports. The pump drive signal excites a common mode of the on-chip Josephson parametric converter.

Abstract translation: 提供了片上约瑟夫逊参数转换器。 片上约瑟夫逊参数转换器包括约瑟夫逊环调制器。 片上约瑟夫逊参数转换器还包括耦合到约瑟夫逊环调制器的无损功率分配器，具有单个输入端口和两个输出端口，用于经由单个输入端口接收泵驱动信号，将泵驱动信号对称地分成两个 在幅度和相位相等的信号，并且从两个输出端口中的相应一个输出两个信号中的每一个。 泵驱动信号激发片上约瑟夫森参数转换器的共模。