公开(公告)号：US20090269922A1

公开(公告)日：2009-10-29

申请号：US12459091

申请日：2009-06-25

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括通过等离子体沉积将金属种子层的第一部分以足够的晶片衬底偏压比与DC源功率沉积在晶片上，达到底部覆盖范围，同时抑制凹陷器件特征的表面的再溅射。 该方法还包括以基板RF偏压的比例将金属种子层的第二部分沉积到DC源功率，使得不会抑制再溅射。

公开(公告)号：US09390970B2

公开(公告)日：2016-07-12

申请号：US11733671

申请日：2007-04-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768 ,  C23C14/04 ,  C23C14/16 ,  H01L21/285

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。第一保护层 的材料通过传统的溅射或离子沉积溅射沉积在衬底表面上，结合足够低的衬底偏压，其中施加了该层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US20100255678A1

公开(公告)日：2010-10-07

申请号：US12802701

申请日：2010-06-11

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。

公开(公告)号：US06758947B2

公开(公告)日：2004-07-06

申请号：US09886439

申请日：2001-06-20

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： C23C1400

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US06488823B1

公开(公告)日：2002-12-03

申请号：US09423470

申请日：1999-11-04

申请人： Tony Chiang ,  Peijun Ding ,  Barry L. Chin ,  Bingxi Sun

发明人： Tony Chiang ,  Peijun Ding ,  Barry L. Chin ,  Bingxi Sun

IPC分类号： C23C1434

CPC分类号： C23C14/345 ,  C23C14/0036 ,  C23C14/0641 ,  C23C14/16 ,  C23C14/3492 ,  C23C14/358 ,  C23C14/5833 ,  H01L21/2855 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure pertains to our discovery that residual stress residing in a tantalum film or tantalum nitride film can be controlled (tuned) during deposition by adjusting at least two particular process variables which have counteracting effects on the residual film stress. By tuning individual film stresses within a film stack, it is possible to balance stresses within the stack. Process variables of particular interest include: power to the sputtering target process chamber pressure (i.e., the concentration of various gases and ions present in the chamber); substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); power to an ionization source (typically a coil); and temperature of the substrate upon which the film is deposited. The process chamber pressure and the substrate offset bias most significantly affect the film tensile and compressive stress components, respectively. The most advantageous tuning of a sputtered film is achieved using high density plasma sputter deposition, which provides for particular control over the ion bombardment of the depositing film surface. When the tantalum or tantalum nitride film is deposited using high density plasma sputtering, power to the ionization source can be varied for stress tuning of the film. We have been able to reduce the residual stress in tantalum or tantalum nitride films deposited using high density plasma sputtering to between about 6×10+9 dynes/cm2 and about −6×10+9 dynes/cm2 using techniques described herein.

摘要翻译： 本公开涉及我们的发现，即通过调节对剩余膜应力具有抵消作用的至少两个特定工艺变量，可以在沉积期间控制（调整）驻留在钽膜或氮化钽膜中的残余应力。 通过调整薄膜叠层内的各个薄膜应力，可以平衡叠层内的应力。 特别感兴趣的过程变量包括：溅射靶处理室压力的功率（即存在于室中的各种气体和离子的浓度）; 衬底DC偏移偏置电压（通常为施加衬底偏置功率的AC增加）; 电源（通常为线圈）; 以及沉积膜的基板的温度。 处理室压力和基板偏移偏压分别最显着地影响膜的拉伸和压应力分量。 使用高密度等离子体溅射沉积来实现溅射膜的最有利的调谐，其提供对沉积膜表面的离子轰击的特定控制。 当使用高密度等离子体溅射沉积钽或氮化钽膜时，电离源的功率可以改变以用于膜的应力调谐。 使用本文所述的技术，我们已经能够将使用高密度等离子体溅射沉积的钽或氮化钽膜中的残余应力减小到约6×10 9 + 9达因/ cm 2和约-6×10 9达因/ cm 2之间。

公开(公告)号：US6139699A

公开(公告)日：2000-10-31

申请号：US863451

申请日：1997-05-27

申请人： Tony Chiang ,  Peijun Ding ,  Barry L. Chin

发明人： Tony Chiang ,  Peijun Ding ,  Barry L. Chin

IPC分类号： C23C14/00 ,  C23C14/06 ,  C23C14/14 ,  C23C14/16 ,  C23C14/34 ,  C23C14/35 ,  C23C14/58 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

CPC分类号： C23C14/345 ,  C23C14/0036 ,  C23C14/0641 ,  C23C14/16 ,  C23C14/3492 ,  C23C14/358 ,  C23C14/5833 ,  H01L21/2855 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002

摘要： The present disclosure pertains to our discovery that residual stress residing in a tantalum film or tantalum nitride film can be controlled (tuned) by controlling particular process variables during film deposition. By tuning individual film stresses within a film stack, it is possible to balance stresses within the stack. Process variables of particular interest include: power to the sputtering target; process chamber pressure (i.e., the concentration of various gases and ions present in the chamber); substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); power to an ionization source (typically a coil); and temperature of the substrate upon which the film is deposited. The process chamber pressure and the substrate offset bias most significantly affect the film tensile and compressive stress components, respectively. The most advantageous tuning of a sputtered film is achieved using high density plasma sputter deposition, which provides for particular control over the ion bombardment of the depositing film surface. When the tantalum or tantalum nitride film is deposited using high density plasma sputtering, power to the ionization source can be varied for stress tuning of the film. We have been able to reduce the residual stress in tantalum or tantalum nitride films deposited using high density plasma sputtering to between about 6.times.10.sup.+9 dynes/cm.sup.2 and about -6.times.10.sup.+9 dynes/cm.sup.2 using techniques described herein. The tantalum and tantalum nitride films can also be tuned following deposition using ion bombardment of the film surface and annealing of the deposited film.

摘要翻译： 本公开涉及我们的发现，通过在膜沉积期间控制特定的工艺变量，可以控制（调整）驻留在钽膜或氮化钽膜中的残余应力。 通过调整薄膜叠层内的各个薄膜应力，可以平衡叠层内的应力。 特别感兴趣的过程变量包括：溅射靶的功率; 处理室压力（即存在于室中的各种气体和离子的浓度）; 衬底DC偏移偏置电压（通常为施加衬底偏置功率的AC增加）; 电源（通常为线圈）; 以及沉积膜的基板的温度。 处理室压力和基板偏移偏压分别最显着地影响膜的拉伸和压应力分量。 使用高密度等离子体溅射沉积来实现溅射膜的最有利的调谐，其提供对沉积膜表面的离子轰击的特定控制。 当使用高密度等离子体溅射沉积钽或氮化钽膜时，电离源的功率可以改变以用于膜的应力调谐。 使用本文所述的技术，我们已经能够将使用高密度等离子体溅射沉积的钽或氮化钽膜中的残余应力减小到约6×10 9 + 9达因/ cm 2和约-6×10 9达因/ cm 2之间。 也可以在使用离子轰击膜表面和沉积膜的退火进行沉积之后调整钽和氮化钽膜。

公开(公告)号：US20090053888A1

公开(公告)日：2009-02-26

申请号：US12288540

申请日：2008-10-20

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/02183 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/02266 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876

摘要： A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer.

摘要翻译： 一种用覆盖的导电层或填充物沉积具有降低半导体器件互连电阻率的渗透阻挡层的方法。 通过诱导在含钽隔离层内形成α钽来实现较低的电阻率。

公开(公告)号：US06793779B2

公开(公告)日：2004-09-21

申请号：US10369856

申请日：2003-02-20

申请人： Peijun Ding ,  Tony Chiang ,  Barry L. Chin

发明人： Peijun Ding ,  Tony Chiang ,  Barry L. Chin

IPC分类号： C23C1434

CPC分类号： H01L21/76877 ,  H01L21/2855

摘要： A method of filling trenches or vias on a semiconductor workpiece surface with copper using sputtering techniques. A copper wetting layer and a copper fill layer may both be applied by sputtering techniques. The thin wetting layer of copper is applied at a substrate surface temperature ranging between about 20° C. to about 250° C., and subsequently the temperature of the substrate is increased, with the application of the sputtered copper fill layer beginning at above at least about 200° C. and continuing while the substrate temperature is increased to a temperature as high as about 600° C. Preferably the substrate temperature during application of the sputtered fill layer ranges between about 300° C. and about 500° C.

摘要翻译： 使用溅射技术用铜填充半导体工件表面上的沟槽或通孔的方法。 铜浸润层和铜填充层都可以通过溅射技术施加。 在约20℃至约250℃范围内的衬底表面温度下施加铜的薄润湿层，随后随着溅射铜填充层的应用从上方开始施加，衬底的温度升高 至少约200℃，并且在衬底温度升高至高达约600℃的温度下继续进行。优选地，溅射填充层施加期间的衬底温度范围为约300℃至约500℃。

公开(公告)号：US08158511B2

公开(公告)日：2012-04-17

申请号：US13068821

申请日：2011-05-20

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface.

摘要翻译： 一种在晶片衬底上沉积具有下层阻挡层的金属种子层的方法，包括多个凹陷的器件特征。 阻挡层的第一部分沉积在晶片衬底上，而不会在与多个凹陷器件特征的开口上过多地形成阻挡层材料，同时获得底部覆盖而无需基本上溅射底部表面。 随后，使用与沉积阻挡层相同的技术沉积金属种子层，以避免金属种子层材料在具有特征的开口上的过度积累，同时阻挡层表面的溅射最少。

公开(公告)号：US07989343B2

公开(公告)日：2011-08-02

申请号：US12802701

申请日：2010-06-11

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。