公开(公告)号：US07476589B2

公开(公告)日：2009-01-13

申请号：US11479117

申请日：2006-06-29

申请人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley

发明人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.

摘要翻译： 场效应晶体管如下形成。 在半导体区域中形成沟槽。 形成衬在沟槽侧壁和底部的电介质层。 沟槽填充有导电材料。 导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。 导电材料的凹陷包括导电材料的各向同性蚀刻。 在凹形屏蔽电极上形成电极间电介质（IED）。

公开(公告)号：US07935577B2

公开(公告)日：2011-05-03

申请号：US12344859

申请日：2008-12-29

申请人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley

发明人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley

IPC分类号： H01L21/8232 ,  H01L21/84 ,  H01L21/00 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

摘要翻译： 在半导体区域中形成沟槽。 形成在沟槽的侧壁和底表面上的介电层。 电介质层沿着下侧壁和底表面比沿着沟槽的上侧壁更厚。 在形成电介质层之后，沟槽的下部填充有屏蔽电极。 电介质间隔物沿着上沟槽侧壁形成。 在形成电介质间隔物之后，在屏蔽电极上的沟槽中形成电极间电介质（IED）。 在形成IED之后，去除电介质间隔物。

公开(公告)号：US08803207B2

公开(公告)日：2014-08-12

申请号：US13081400

申请日：2011-04-06

申请人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

发明人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

IPC分类号： H01L29/76 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.

摘要翻译： 在一个一般方面，一种装置可以包括设置在半导体区域中的沟槽，衬在沟槽的侧壁的下部的屏蔽电介质层和沟槽的底表面，以及衬在该侧壁的上部的栅极电介质 的沟槽。 该设备还可以包括设置在沟槽的下部并由屏蔽电介质层与半导体区域绝缘​​的屏蔽电极，以及设置在屏蔽电极上的沟槽中的电极间电介质（IED），其中屏蔽电极具有 一个弯曲的顶面。

公开(公告)号：US20110212586A1

公开(公告)日：2011-09-01

申请号：US13081400

申请日：2011-04-06

申请人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

发明人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A method for forming a field effect transistor includes forming a trench in a semiconductor region and forming a dielectric layer lining lower sidewalls and bottom surface of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation and carrying out a dry ambient oxidation. A gate electrode is formed in an upper portion of the trench. The gate electrode may be insulated from the shield electrode by the IED.

摘要翻译： 用于形成场效应晶体管的方法包括在半导体区域中形成沟槽，并形成衬在沟槽的下侧壁和底表面的电介质层。 在形成电介质层之后，沟槽的下部填充有屏蔽电极。 通过进行蒸汽环境氧化并进行干燥环境氧化，在屏蔽电极上的沟槽中形成电极间电介质（IED）。 栅电极形成在沟槽的上部。 栅电极可以通过IED与屏蔽电极绝缘。

公开(公告)号：US20090111231A1

公开(公告)日：2009-04-30

申请号：US12344859

申请日：2008-12-29

申请人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

发明人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

摘要翻译： 在半导体区域中形成沟槽。 形成在沟槽的侧壁和底表面上的介电层。 电介质层沿着下侧壁和底表面比沿着沟槽的上侧壁更厚。 在形成电介质层之后，沟槽的下部填充有屏蔽电极。 电介质间隔物沿着上沟槽侧壁形成。 在形成电介质间隔物之后，在屏蔽电极上的沟槽中形成电极间电介质（IED）。 在形成IED之后，去除电介质间隔物。

公开(公告)号：US11458376B2

公开(公告)日：2022-10-04

申请号：US17113839

申请日：2020-12-07

申请人： Curtis Jaques ,  Rodney Ridley

发明人： Curtis Jaques ,  Rodney Ridley

IPC分类号： A63B63/00 ,  A63B69/00 ,  A63B102/14

摘要： A mobile, free standing field sport shooting target device, including a pole having a first end and a second end, wherein an opening is located at the first and second ends of the pole, a counter weight plate having a plurality of openings, wherein the counter weight plate is located adjacent to the first end of the pole, and a collar operatively connected to the first end of the pole, wherein the collar has a first end and a second end such that the counter weight plate is located adjacent to the first end of the collar and the collar is used to retain the counter weight on the first end of the pole, and wherein a distance between the first end of the pole and the second end of the collar can be adjusted.

公开(公告)号：US20070155104A1

公开(公告)日：2007-07-05

申请号：US11327657

申请日：2006-01-05

申请人： Bruce Marchant ,  Thomas Grebs ,  Rodney Ridley ,  Nathan Kraft

发明人： Bruce Marchant ,  Thomas Grebs ,  Rodney Ridley ,  Nathan Kraft

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7811 ,  H01L21/3083 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7813 ,  Y10S438/942 ,  Y10S438/95

摘要： A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.

摘要翻译： 沟槽门控场效应晶体管（FET）如下形成。 使用一个掩模，多个有源栅极沟槽和至少一个栅极流道沟槽被限定并同时形成在硅区域中，使得（i）至少一个栅极流道沟槽的宽度大于多个栅极沟槽的宽度 的有源栅极沟槽，以及（ii）多个有源栅极沟槽与至少一个栅极流道沟槽邻接。

公开(公告)号：US20070082441A1

公开(公告)日：2007-04-12

申请号：US11551992

申请日：2006-10-23

申请人： Nathan Kraft ,  Ashok Challa ,  Steven Sapp ,  Hamza Yilmaz ,  Daniel Calafut ,  Dean Probst ,  Rodney Ridley ,  Thomas Grebs ,  Christopher Kocon ,  Joseph Yedinak ,  Gary Dolny

发明人： Nathan Kraft ,  Ashok Challa ,  Steven Sapp ,  Hamza Yilmaz ,  Daniel Calafut ,  Dean Probst ,  Rodney Ridley ,  Thomas Grebs ,  Christopher Kocon ,  Joseph Yedinak ,  Gary Dolny

IPC分类号： H01L21/8242

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

摘要翻译： 场效应晶体管如下形成。 沟槽形成在第一导电类型的半导体区域中。 每个沟槽部分地填充有一种或多种材料。 执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。 进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻的沟槽之间形成第二导电类型的体区。 然后在每个身体区域中形成第一导电类型的源区域。

公开(公告)号：US20060273386A1

公开(公告)日：2006-12-07

申请号：US11441386

申请日：2006-05-24

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Kocon ,  Steven Sapp ,  Dean Probst ,  Nathan Kraft ,  Thomas Grebs ,  Rodney Ridley ,  Gary Dolny ,  Bruce Marchant ,  Joseph Yedinak

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Kocon ,  Steven Sapp ,  Dean Probst ,  Nathan Kraft ,  Thomas Grebs ,  Rodney Ridley ,  Gary Dolny ,  Bruce Marchant ,  Joseph Yedinak

IPC分类号： H01L29/94

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

摘要翻译： 场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。 栅极沟槽延伸穿过身体区域并终止在半导体区域内。 至少一个导电屏蔽电极设置在栅极沟槽中。 栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。 屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。 栅极电介质层使栅电极与体区绝缘。 屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

公开(公告)号：US20060214221A1

公开(公告)日：2006-09-28

申请号：US11445020

申请日：2006-05-31

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.