公开(公告)号：US4373138A

公开(公告)日：1983-02-08

申请号：US232011

申请日：1981-02-06

Applicant: Theodore A. Fulton ,  Arthur F. Hebard

Inventor： Theodore A. Fulton ,  Arthur F. Hebard

IPC: H03K3/38

CPC classification number: H03K3/38 ,  Y10S505/864

Abstract: Described is a DC powered flip-flop logic or memory element (i.e., circuit) which comprises two Josephson junction gates J.sub.1 and J.sub.2 which operate individually in the latching mode. In one logic state, the gate J.sub.1 is at V.sub.1 =O while J.sub.2 is at V.sub.2 .noteq.O. In the other logic state, the roles of the two junctions are reversed. The two junctions are interconnected by a passive network such that the switching of J.sub.2, say, from V.sub.2 =O to V.sub.2 .noteq.O induces a current-voltage transient on J.sub.1 which returns it to V.sub.1 =O, and conversely.

Abstract translation: 描述了一种直流供电的触发器逻辑或存储元件（即，电路），其包括两个在锁存模式下分别操作的约瑟夫逊结门J1和J2。 在一个逻辑状态下，门J1为V1 = 0，而J2为V2 NOTEQUAL O.在另一个逻辑状态下，两个结的作用相反。 两个结通过无源网络相互连接，使得J2的切换从V2 = O到V2 NOTEQUAL O在J1上引起电流电压瞬变，将其返回到V1 = 0，反之亦然。

公开(公告)号：US4400631A

公开(公告)日：1983-08-23

申请号：US233949

申请日：1981-02-12

Applicant: Theodore A. Fulton

Inventor： Theodore A. Fulton

IPC: H03K17/92 ,  H03K19/195 ,  H03K3/38

CPC classification number: H03K17/92 ,  H03K19/1952 ,  Y10S505/861

Abstract: A superconductive circuit is described for diverting bias current to an output line in response to magnetic field control means. A first plurality of branches containing magnetically switchable Josephson junction gates are connected in parallel, and a second plurality of the same gates, less than or equal in number to the first plurality, are actuated essentially simultaneously by the control means. As a consequence, high-gain, high-speed operation is made possible.

Abstract translation: 描述了用于响应于磁场控制装置将偏置电流转移到输出线的超导电路。 并联地连接包含可磁性切换的约瑟夫逊结门的第一多个分支，并且数量小于或等于第一多个的第二多个相同的栅极基本上由控制装置同时被致动。 因此，高增益高速运行成为可能。

公开(公告)号：USRE35119E

公开(公告)日：1995-12-12

申请号：US820730

申请日：1992-01-14

Applicant: Greg E. Blonder ,  Theodore A. Fulton

Inventor： Greg E. Blonder ,  Theodore A. Fulton

IPC: H01L21/60 ,  H01L23/13 ,  H01L23/14 ,  H01L23/485 ,  H01L23/48 ,  H01L23/02 ,  H01L23/16 ,  H01L23/42

CPC classification number: H01L23/147 ,  H01L23/13 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L24/98 ,  H01L2224/13 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/29144 ,  H01L2224/45144 ,  H01L2224/8103 ,  H01L2224/81205 ,  H01L2224/81224 ,  H01L2224/81385 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3511

Abstract: Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon career, and depositing the gold on the silicon dioxide layer.

Abstract translation: 集成电路芯片到芯片的互连是通过每个芯片上的金焊盘制成的，其结合到硅晶片芯片载体上的对应的金焊盘。 芯片上的焊盘和/或载体上的焊盘的特征在于纹理（粗糙化），其特征尺寸为千微米或更小的量级，使得芯片上的每个焊盘可以附接到每个焊盘 在载体上通过室温下的压接，即冷阱粘合。 特别地，硅载体上的金焊盘的纹理通过在焊盘的区域中的下面的硅载体的表面上局部蚀刻V形槽来获得，在硅工业上热生长二氧化硅层，并将 金在二氧化硅层上。

公开(公告)号：US5149404A

公开(公告)日：1992-09-22

申请号：US628253

申请日：1990-12-14

Applicant: Greg E Blonder ,  Theodore A. Fulton

Inventor： Greg E Blonder ,  Theodore A. Fulton

IPC: C25F3/12 ,  C25F3/14 ,  H05K3/08

CPC classification number: H05K3/08 ,  C25F3/12 ,  C25F3/14

Abstract: Fine lines (approximately 3 microns or less) are patternable on conductive materials by electromachining techniques. These micro-techniques differ from conventional electromachining in that the linewidth is primarily determined by the characteristics of the electric field rather than the electrode geometry.

Abstract translation: 细线（约3微米或更小）可通过电子加工技术在导电材料上进行图案化。 这些微技术不同于传统的电加工，因为线宽主要由电场的特性决定，而不是电极几何形状。

公开(公告)号：US4937653A

公开(公告)日：1990-06-26

申请号：US222465

申请日：1988-07-21

Applicant: Greg E. Blonder ,  Theodore A. Fulton

Inventor： Greg E. Blonder ,  Theodore A. Fulton

IPC: H01L21/60 ,  H01L23/13 ,  H01L23/14 ,  H01L23/485

CPC classification number: H01L23/147 ,  H01L23/13 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L24/98 ,  H01L2224/13 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/29144 ,  H01L2224/45144 ,  H01L2224/8103 ,  H01L2224/81205 ,  H01L2224/81224 ,  H01L2224/81385 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3511

Abstract: Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer.

公开(公告)号：US4470190A

公开(公告)日：1984-09-11

申请号：US445290

申请日：1982-11-29

Applicant: Theodore A. Fulton ,  Shin-Shem Pei

Inventor： Theodore A. Fulton ,  Shin-Shem Pei

IPC: H01L39/24 ,  H01L39/22 ,  H01L21/265

CPC classification number: H01L39/2493 ,  Y10S505/922

Abstract: A method for changing Josephson device parameters, e.g., the critical current of a Josephson junction. The method comprises incorporating doping material into the device, or part of the device, followed by a light anneal. Exemplary dopants include In, Sn, Sb, Te, Bi, Hg, Mg, Li, Cd, Na and Ta, with In, Sn, and Sb being preferred dopants for changing the critical current of a Josephson junction having a Pb-containing counter electrode. The dopant can be incorporated into the device by in-diffusion after deposition onto the surface, by ion implantation, or by any other convenient method. The amount of dopant required is typically small. For example, deposition of a Sn layer of 0.05 nm effective thickness onto the 200 nm thick Pb-Sb(1.5 wt. %) counter electrode of a cross-type Josephson junction, and annealing at 80.degree. C. for about 3 hours, resulted in an increase in the critical current of the junction by a factor of about 2.5. The method is considered to have wide applicability in the manufacture of Josephson devices, and can be applied globally, i.e., to all the devices on a wafer or chip, or locally, i.e., to selected devices.

Abstract translation: 一种用于改变约瑟夫逊器件参数的方法，例如约瑟夫逊结的临界电流。 该方法包括将掺杂材料掺入器件或器件的一部分，随后进行轻退火。 示例性的掺杂剂包括In，Sn，Sb，Te，Bi，Hg，Mg，Li，Cd，Na和Ta，其中In，Sn和Sb是用于改变具有含Pb计数器的约瑟夫逊结的临界电流的优选掺杂剂 电极。 通过在表面上沉积后，通过离子注入或通过任何其它方便的方法，掺杂剂可以通过扩散进入装置。 所需的掺杂剂的量通常很小。 例如，将0.05nm有效厚度的Sn层沉积到交叉型约瑟夫逊结的200nm厚的Pb-Sb（1.5重量％）对电极上，并在80℃退火约3小时，得到 在连接的临界电流增加约2.5倍。 该方法被认为在约瑟夫逊器件的制造中具有广泛的应用，并且可以全局地应用于晶片或芯片上的所有器件，或局部应用于所选器件。

公开(公告)号：US4275314A

公开(公告)日：1981-06-23

申请号：US34569

申请日：1979-04-30

Applicant: Theodore A. Fulton

Inventor： Theodore A. Fulton

IPC: H03K3/38 ,  H03K17/92 ,  H03K19/195 ,  H03K19/20

CPC classification number: H03K19/1956 ,  H03K17/92 ,  H03K19/1954 ,  H03K3/38 ,  Y10S505/859 ,  Y10S505/861

Abstract: A current-switched gate is described which comprises two Josephson tunnel junctions and a small resistor in a triangular loop. Directly combined bias and control currents flow through one junction in the zero-voltage state, causing the switching. The second junction and the resistor provide isolation between input and output after switching. Switching speeds of a few tens of picoseconds and the microwatt power dissipation are attained. Latching as well as nonlatching schemes and memory circuits are described.

Abstract translation: 描述了一个电流切换门，其包括两个约瑟夫逊隧道结和三角形环路中的小电阻。 直接组合的偏置和控制电流在零电压状态下流过一个结，导致开关。 第二个接点和电阻在切换后提供输入和输出之间的隔离。 达到几十皮秒的开关速度和微瓦功率消耗。 描述了锁存以及非锁存方案和存储器电路。

公开(公告)号：US4249094A

公开(公告)日：1981-02-03

申请号：US965327

申请日：1978-12-01

Applicant: Theodore A. Fulton

Inventor： Theodore A. Fulton

IPC: H03K19/195 ,  H03K19/20

CPC classification number: H03K19/1952 ,  Y10S505/864

Abstract: A DC powered, self-resetting Josephson junction logic circuit relying on relaxation oscillations is described. A pair of Josephson junction gates are connected in series, a first shunt is connected in parallel with one of the gates, and a second shunt is connected in parallel with the series combination of gates. The resistance of the shunts and the DC bias current bias the gates so that they are capable of undergoing relaxation oscillations. The first shunt forms an output line whereas the second shunt forms a control loop. The bias current is applied to the gates so that, in the quiescent state, the gate in parallel with the second shunt is at V=O, and the other gate is undergoing relaxation oscillations. By controlling the state of the first gate with the current in the output loop of another identical circuit, the invert function is performed.

Abstract translation: 描述了依赖于松弛振荡的直流供电的自复位约瑟夫逊结逻辑电路。 一对约瑟夫逊结门串联连接，第一分路与其中一个栅极并联连接，第二分路与门的串联组合并联连接。 分流器的电阻和直流偏置电流使栅极偏置，使得它们能够经历弛豫振荡。 第一分路形成输出线，而第二分路形成控制回路。 偏置电流被施加到栅极，使得在静止状态下，与第二分路并联的栅极为V = O，而另一栅极正在经历弛豫振荡。 通过利用另一相同电路的输出回路中的电流来控制第一门的状态，执行反转功能。