-
1.发明授权公开(公告)号：US09432044B1
公开(公告)日：2016-08-30
申请号：US14973902
申请日：2015-12-18
发明人： Seung Bae Lee , Ajit Sharma , Srinath Ramaswamy
CPC分类号： H03M1/1061 , H03M1/468 , H03M1/687
摘要： A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) is calibrated by determining an error voltage for each of a plurality of most significant bit (MSB) capacitors in a first segment using a calibration DAC. The first segment is connected to the second segment by an attenuation capacitor. Each of the error voltages corresponding to the MSB capacitors is digitized to form a set of digitized error voltages. An error voltage for each of a plurality of less significant bit (LSB) capacitors in at least the second segment is calculated by summing the set of digitized error voltages to form a sum of error voltages (sum(e)) and assigning a percentage of sum(e) as the error voltage for each of the LSB capacitors, such that a mismatch in the attenuation capacitor is mitigated.
摘要翻译： 通过使用校准DAC确定第一段中的多个最高有效位（MSB）电容器中的每一个的误差电压来校准多段电容逐次逼近模数转换器（SAR ADC）。 第一段通过衰减电容器连接到第二段。 对应于MSB电容器的每个误差电压被数字化以形成一组数字化的误差电压。 至少第二段中的多个较低有效位（LSB）电容器中的每一个的误差电压通过将数字化误差电压的集合相加以形成误差电压（sum（e））的和并且分配 总和（e）作为每个LSB电容器的误差电压，使得减小衰减电容器的失配。
-
公开(公告)号：US09397685B1
公开(公告)日：2016-07-19
申请号：US14806826
申请日：2015-07-23
CPC分类号： H03M1/1245
摘要： Described examples include low power analog front end circuits for sensing repeating signal waveforms, including a first sampling circuit to sample an input signal, an analog detector circuit to provide a detector output signal representing a feature of the input signal, a second sampling circuit to sample the detector output signal, and a control circuit to control a sample rate or other analog front end operating parameter at least partially according to the sampled detector output signal, and to selectively enable and disable the analog detector circuit at least partially according to a model representing an expected repeating waveform of the input signal.
摘要翻译： 所描述的示例包括用于感测重复信号波形的低功率模拟前端电路，包括用于对输入信号进行采样的第一采样电路，模拟检测器电路，以提供表示输入信号特征的检测器输出信号，第二采样电路 检测器输出信号，以及控制电路，用于至少部分地根据采样的检测器输出信号来控制采样率或其他模拟前端工作参数，并且至少部分地根据代表的模型来选择性地启用和禁用模拟检测器电路 预期的输入信号的重复波形。
-
公开(公告)号：US09319059B1
公开(公告)日：2016-04-19
申请号：US14732676
申请日：2015-06-06
CPC分类号： H03M1/46 , H03M1/1057 , H03M1/38 , H03M1/403 , H03M1/468
摘要： The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) (100) is substantially reduced by using a number of shared capacitors (SC1-SCs−1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.
摘要翻译： 基于校准电容器的逐次逼近寄存器（SAR）模数转换器（ADC）（100）的半导体制造所需的硅绝缘体通过使用多个共用电容器（SC1-SCs-1）而大大降低， 它们在校准模式下工作时用作校准电容器，在正常模式下工作时用作位电容器。
-
4.发明申请Methods and Apparatus for Reducing Noise, Power and Settling Time in Multi-Modal Analog Multiplexed Data Acquisition Systems 有权用于降低多模态模拟多路复用数据采集系统中噪声，功率和稳定时间的方法和装置公开(公告)号：US20160380660A1
公开(公告)日：2016-12-29
申请号：US15084052
申请日：2016-03-29
发明人： Arup Polley , Ajit Sharma , Seung Bae Lee , Sriram Narayanan , Srinath Ramaswamy
IPC分类号： H04B1/10
CPC分类号： H04B1/1036 , H04B1/0028 , H04B2001/1054
摘要： Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.
摘要翻译： 在多模式模拟复用数据采集系统中，通过快速建立时间和更高性能降低噪声和功耗。 示例性装置配置包括被配置为接收多个模拟输入信号的电路输入; 模数转换器电路，被配置为输出模拟电压的数字表示; 选择电路，被配置为选择在所述电路输入处接收的所述模拟输入信号之一; 耦合以接收所选择的一个模拟输入信号的缓冲器; 滤波器，耦合到所述缓冲器并且被配置为响应于控制信号执行高带宽采样操作和低带宽采样操作并具有滤波器输出; 以及耦合到所述滤波器以对所述滤波器输出进行采样并且具有耦合到所述模数转换器的输出的采样电容器。 公开了方法和附加装置布置。
-
公开(公告)号：US09007244B2
公开(公告)日：2015-04-14
申请号：US14321434
申请日：2014-07-01
CPC分类号： H03M1/124 , H03M1/002 , H03M1/1255 , H03M1/126
摘要： A mixed signal device includes an analog circuit and a digital circuit coupled to the analog circuit. The digital circuit includes a component that samples a signal at a sampling rate that is dynamically variable by the digital circuit based on the bandwidth of the incoming signal. The digital circuit is to automatically assert a signal to the analog circuit to change a bias current of the analog circuit based on a change to the sampling rate in the digital circuit.
摘要翻译： 混合信号装置包括模拟电路和耦合到模拟电路的数字电路。 数字电路包括以基于输入信号的带宽由数字电路动态变化的采样率对信号进行采样的部件。 数字电路是根据数字电路中采样率的变化，自动向模拟电路断言信号以改变模拟电路的偏置电流。
-
公开(公告)号：US20170301726A1
公开(公告)日：2017-10-19
申请号：US15639327
申请日：2017-06-30
发明人： Keith Ryan Green , Rajni J. Aggarwal , Ajit Sharma
CPC分类号： H01L27/22 , H01L43/04 , H01L43/065 , H01L43/14
摘要： A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.
-
公开(公告)号：US09742420B2
公开(公告)日：2017-08-22
申请号：US14954577
申请日：2015-11-30
发明人： Sriram Narayanan , Srinath Ramaswamy , Arup Polley , Ajit Sharma
CPC分类号： H03M1/0609 , H03M1/001 , H03M1/002 , H03M1/1295 , H03M1/162
摘要： An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.
-
公开(公告)号：US09717426B2
公开(公告)日：2017-08-01
申请号：US14837179
申请日：2015-08-27
发明人： Ajit Sharma , Sriram Narayanan , Srinath Mathur Ramaswamy , Arup Polley , Seung Bae Lee , Wen Li
CPC分类号： A61B5/02427 , A61B5/6826 , A61B5/7228 , A61B2562/0238
摘要： The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.
-
公开(公告)号：US20170125479A1
公开(公告)日：2017-05-04
申请号：US14932949
申请日：2015-11-04
发明人： Keith Ryan Green , Rajni J. Aggarwal , Ajit Sharma
CPC分类号： H01L27/22 , H01L43/04 , H01L43/065 , H01L43/14
摘要： A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.
-
公开(公告)号：US09615427B1
公开(公告)日：2017-04-04
申请号：US14954618
申请日：2015-11-30
发明人： Sriram Narayanan , Srinath Ramaswamy , Arup Polley , Ajit Sharma
IPC分类号： H05B37/02 , A61B5/00 , H05B33/08 , A61B5/024 , A61B5/1455
CPC分类号： H05B37/0218 , A61B5/02416 , A61B5/14551 , A61B5/7203 , H05B33/0854 , H05B37/0281 , Y02B20/46
摘要： An optical system includes an optical illumination source, an optical receiver, a correlation determination circuit, and an ambient condition control circuit. The optical illumination source is configured to emit a light in the direction of a target object. The optical receiver is configured to receive a combined optical signal that includes an ambient light component combined with an interrogation component. The correlation determination circuit is configured to compare the combined optical signal with an ambient light signal to identify a correlation factor. The ambient condition control circuit is configured to compare the correlation factor to a low correlation threshold value and a high correlation threshold value, and, based on the correlation factor exceeding the low threshold value and being less than the high correlation threshold value, cancel the ambient light component from the combined optical signal to produce an interrogation signal including the interrogation component.
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.021 秒)
