公开(公告)号：US08647972B1

公开(公告)日：2014-02-11

申请号：US13618255

申请日：2012-09-14

Applicant: Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

Abstract translation: 实施例涉及场效应晶体管（FET）替换门装置。 该装置包括一个或多个衬底和绝缘体，其包括限定沟槽的基底和侧壁。 在沟槽的底壁和侧壁上形成高介电常数（高k）层。 高k层具有与沟槽形状一致的上表面。 第一层形成在高k层上并符合沟槽的形状。 第一层包括无铝的金属氮化物。 在第一层上形成第二层并符合沟槽的形状。 第二层包括铝和至少一种其他金属。 第三层形成在第二层上并符合沟槽的形状。 第三层包括无铝金属氮化物。

公开(公告)号：US20140070307A1

公开(公告)日：2014-03-13

申请号：US13615343

申请日：2012-09-13

Applicant: Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

IPC: H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

Abstract translation: 实施例涉及场效应晶体管（FET）替换门装置。 该装置包括一个通道结构，该通道结构包括限定沟槽的底座和侧壁。 在沟槽的底壁和侧壁上形成高介电常数（高k）层。 高k层具有与沟槽形状一致的上表面。 第一层形成在高k层上并符合沟槽的形状。 第一层包括无铝的金属氮化物。 在第一层上形成第二层并符合沟槽的形状。 第二层包括铝和至少一种其它金属。 第三层形成在第二层上并符合沟槽的形状。 第三层包括无铝金属氮化物。

公开(公告)号：US08659077B1

公开(公告)日：2014-02-25

申请号：US13615343

申请日：2012-09-13

Applicant: Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

Abstract translation: 实施例涉及场效应晶体管（FET）替换门装置。 该装置包括一个通道结构，该通道结构包括限定沟槽的底座和侧壁。 在沟槽的底壁和侧壁上形成高介电常数（高k）层。 高k层具有与沟槽形状一致的上表面。 第一层形成在高k层上并符合沟槽的形状。 第一层包括无铝的金属氮化物。 在第一层上形成第二层并符合沟槽的形状。 第二层包括铝和至少一种其他金属。 第三层形成在第二层上并符合沟槽的形状。 第三层包括无铝金属氮化物。

公开(公告)号：US08716813B2

公开(公告)日：2014-05-06

申请号：US13556333

申请日：2012-07-24

Applicant: Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

Inventor： Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L29/78

CPC classification number: H01L21/823842 ,  H01L21/02164 ,  H01L21/02697 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/518

Abstract: A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.

Abstract translation: 场效应晶体管器件包括：第一栅堆叠部分，包括设置在衬底上的电介质层，设置在电介质层上的第一TiN层，设置在电介质层上的金属层和设置在金属层上的第二TiN层， 与第一栅叠层部相邻设置的第一源极区域和与第一栅极堆叠部分相邻设置的第一漏极区域。

公开(公告)号：US20120139053A1

公开(公告)日：2012-06-07

申请号：US12960586

申请日：2010-12-06

Applicant: Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7848

Abstract: A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

Abstract translation: 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。

公开(公告)号：US08420473B2

公开(公告)日：2013-04-16

申请号：US12960586

申请日：2010-12-06

Applicant: Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7848

Abstract: A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

Abstract translation: 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。

公开(公告)号：US20120181630A1

公开(公告)日：2012-07-19

申请号：US13006656

申请日：2011-01-14

Applicant: Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

公开(公告)号：US20100187610A1

公开(公告)日：2010-07-29

申请号：US12359520

申请日：2009-01-26

Applicant: Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

Inventor： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

Abstract translation: 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

公开(公告)号：US08716118B2

公开(公告)日：2014-05-06

申请号：US13345295

申请日：2012-01-06

Applicant: Takashi Ando ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/3205

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

Abstract: A transistor includes a semiconductor layer and a gate structure located on the semiconductor layer. The gate structure includes a first dielectric layer. The first dielectric layer includes a doped region and an undoped region below the doped region. A second dielectric layer is located on the first dielectric layer, and a first metal nitride layer is located on the second dielectric layer. The doped region of the first dielectric layer comprises dopants from the second dielectric layer. Source and drain regions in the semiconductor layer are located on opposite sides of the gate structure.

Abstract translation: 晶体管包括位于半导体层上的半导体层和栅极结构。 栅极结构包括第一介电层。 第一介电层包括掺杂区域和掺杂区域下面的未掺杂区域。 第二电介质层位于第一电介质层上，第一金属氮化物层位于第二电介质层上。 第一介电层的掺杂区域包括来自第二介电层的掺杂剂。 半导体层中的源极和漏极区位于栅极结构的相对侧上。

公开(公告)号：US08716088B2

公开(公告)日：2014-05-06

申请号：US13534573

申请日：2012-06-27

Applicant: Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

Inventor： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.