公开(公告)号：US20190305097A1

公开(公告)日：2019-10-03

申请号：US16442964

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre COLINGE ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/417 ,  H01L29/775 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/41 ,  H01L21/285 ,  H01L29/06 ,  B82Y40/00

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

公开(公告)号：US20190103322A1

公开(公告)日：2019-04-04

申请号：US16205419

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng CHING ,  Carlos H. DIAZ ,  Jean-Pierre COLINGE

IPC: H01L21/8238 ,  H01L29/06 ,  B82Y40/00 ,  H01L29/786 ,  H01L29/16 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775 ,  B82Y10/00

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US20190337800A1

公开(公告)日：2019-11-07

申请号：US16416545

申请日：2019-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre COLINGE ,  Ta-Pen GUO ,  Chih-Hao WANG ,  Carlos H. DIAZ

IPC: B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  B82Y40/00 ,  H01L29/66

Abstract: A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.

公开(公告)号：US20180269321A1

公开(公告)日：2018-09-20

申请号：US15983444

申请日：2018-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre COLINGE ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/32139 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

公开(公告)号：US20180002172A1

公开(公告)日：2018-01-04

申请号：US15705359

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre COLINGE ,  Ta-Pen GUO ,  Chih-Hao WANG ,  Carlos H. DIAZ

IPC: B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.

公开(公告)号：US20180323284A1

公开(公告)日：2018-11-08

申请号：US16022880

申请日：2018-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ ,  Yeh HSU ,  Tsung-Hsing YU ,  Chia-Wen LIU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L21/225 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66712 ,  H01L21/2251 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66787 ,  H01L29/7391 ,  H01L29/785

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.