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公开(公告)号:US20170221765A1
公开(公告)日:2017-08-03
申请号:US15485270
申请日:2017-04-12
Inventor: Kuo-Cheng CHING , Guan-Lin CHEN
IPC: H01L21/8234 , H01L27/088
CPC classification number: H01L21/823431 , H01L21/823468 , H01L21/823481 , H01L27/0886 , H01L29/66545 , H01L29/6656 , H01L29/66818 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/785
Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.
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2.
公开(公告)号:US20210407993A1
公开(公告)日:2021-12-30
申请号:US16910488
申请日:2020-06-24
Inventor: Shi Ning JU , Kuo-Cheng CHIANG , Chih-Hao WANG , Kuan-Lun CHENG , Guan-Lin CHEN
IPC: H01L27/088 , H01L29/417 , H01L29/78 , H01L29/66 , H01L29/16 , H01L29/06
Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
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3.
公开(公告)号:US20250098293A1
公开(公告)日:2025-03-20
申请号:US18971477
申请日:2024-12-06
Inventor: Shi Ning JU , Kuo-Cheng CHIANG , Chih-Hao WANG , Kuan-Lun CHENG , Guan-Lin CHEN
IPC: H01L27/088 , H01L29/06 , H01L29/16 , H01L29/417 , H01L29/66 , H01L29/78
Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
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4.
公开(公告)号:US20230369326A1
公开(公告)日:2023-11-16
申请号:US18360889
申请日:2023-07-28
Inventor: Shi Ning JU , Kuo-Cheng CHIANG , Chih-Hao WANG , Kuan-Lun CHENG , Guan-Lin CHEN
IPC: H01L27/088 , H01L29/417 , H01L29/78 , H01L29/16 , H01L29/06 , H01L29/66
CPC classification number: H01L27/0886 , H01L29/41791 , H01L29/785 , H01L29/16 , H01L29/0665 , H01L29/0653 , H01L29/66795 , H01L2029/7858
Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
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5.
公开(公告)号:US20220231017A1
公开(公告)日:2022-07-21
申请号:US17712255
申请日:2022-04-04
Inventor: Shi Ning JU , Kuo-Cheng CHIANG , Chih-Hao WANG , Kuan-Lun CHENG , Guan-Lin CHEN
IPC: H01L27/088 , H01L29/417 , H01L29/78 , H01L29/16 , H01L29/06 , H01L29/66
Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
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