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    Method for forming semiconductor device structure with gate
    4.
    发明授权
    Method for forming semiconductor device structure with gate 有权

    公开(公告)号：US10522411B2

    公开(公告)日：2019-12-31

    申请号：US15791289

    申请日：2017-10-23

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chai-Wei Chang ,  Po-Chi Wu ,  Wen-Han Fang

    IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L21/3105

    摘要： A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.

    Semiconductor Device and Method of Manufacture
    5.
    发明申请
    Semiconductor Device and Method of Manufacture 有权
    半导体器件及其制造方法

    公开(公告)号：US20160043079A1

    公开(公告)日：2016-02-11

    申请号：US14578188

    申请日：2014-12-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chai-Wei Chang ,  Po-Chi Wu ,  Che-Cheng Chang

    IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L27/0886 ,  H01L21/02068 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/823456 ,  H01L29/0649 ,  H01L29/4232 ,  H01L29/785

    摘要： In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged.

    摘要翻译： 根据一些实施例，导电材料从第一多个翅片和第二多个翅片上移除，其中第一多个翅片位于小的栅极长度区域内，并且第二多个鳍片位于较大的栅极长度 地区。 通过最初执行具有低压和高流速的至少一种蚀刻剂的干蚀刻来执行去除，这使得导电材料在第二多个翅片上比在第一多个翅片上具有更大的厚度。 这样，当利用湿蚀刻去除导电材料的其余部分时，第二组散热片与导电材料之间的电介质材料不被损坏。